Sensing amplifier comprising bias circuitry coupled to bit line and dummy bitline for performing read operation in flash memory devices

A non-volatile memory device comprising:

• a first array of flash memory cells;
• a selected bit line coupled to a selected flash memory cell in the first array;
• a second array of flash memory cells;
• a dummy bit line coupled to a dummy flash memory cell in the second array;
• and
• a sensing amplifier comprising:
• a comparator;
• and
• a first capacitor coupled between the selected bit line and the comparator and a second capacitor coupled between the dummy bit line and the comparator, the first capacitor and second capacitor having different capacitance values;
• wherein during a read operation the first capacitor initially provides a bias voltage to the selected bit line and the second capacitor initially provides a bias voltage to the dummy bit line and over time the first capacitor and second capacitor discharge at different rates in proportion to the different capacitance values.