Write enable circuit, access switching circuit and analog-to-digital converter unit

An access switching circuit that switches an access mode, in an analog-to-digital converter unit comprising a bus control unit connected to an external unit, an arithmetic processing unit to perform data processing, and an arithmetic unit to hold digital data obtained by analog-to-digital conversion, and having a normal access mode in which the digital data are temporarily written into the arithmetic processing unit and then written into the bus control unit and a high-speed access mode in which the digital data are written directly into the bus control unit, the access switching circuit comprising:

• a logical OR circuit to perform an OR operation of a normal access signal indicating that now is in the normal access mode and a high-speed access signal indicating that now is in the high-speed access mode, which are outputted by the arithmetic processing unit, and output a result of the OR operation to the bus control unit;
• a first logic circuit to input a read signal from the arithmetic processing unit to the bus control unit only when the arithmetic processing unit asserts the normal access signal;
• and
• a second logic circuit to input a write signal from the arithmetic processing unit to the bus control unit only when the arithmetic processing unit asserts the normal access signal.

An analog-to-digital converter unit comprising a bus control unit connected to an external unit, an arithmetic processing unit to perform data processing, and an arithmetic unit to hold digital data obtained by analog-to-digital conversion, and having a normal access mode in which the digital data are temporarily written into the arithmetic processing unit and then written into the bus control unit and a high-speed access mode in which the digital data are written directly into the bus control unit, the analog-to-digital converter unit comprising:

• a logical OR circuit to perform an OR operation of a normal access signal indicating that now is in the normal access mode and a high-speed access signal indicating that now is in the high-speed access mode, which are outputted by the arithmetic processing unit, and output a result of the OR operation to the bus control unit;
• a first logic circuit to input a read signal from the arithmetic processing unit to the bus control unit only when the arithmetic processing unit asserts the normal access signal;
• a second logic circuit to input a write signal from the arithmetic processing unit to the bus control unit only when the arithmetic processing unit asserts the normal access signal;
• an address coincidence determining circuit provided in the arithmetic unit to output a write enable signal from the arithmetic unit when a predetermined address for a memory of the bus control unit coincides with an address designated by the arithmetic processing unit;
• and
• a third logic circuit to input the write enable signal to the bus control unit only when the arithmetic processing unit asserts the high-speed access signal.