Dual loop adaptive LDO voltage regulator

A method comprising:

• providing a source voltage to a low drop-out (LDO) voltage regulator comprising a voltage loop and a current loop;
• controlling an output voltage of the LDO voltage regulator using the voltage loop, the voltage loop having an amplifier circuit coupled to a gate terminal of a first PMOS transistor of a source follower in the current loop, wherein a source of the first PMOS transistor is coupled to an output node of the LDO voltage regulator;
• and
• controlling a load current using the current loop, the current loop further comprising a current mirror, wherein the current mirror comprises second and third PMOS transistors, wherein the second PMOS transistor is diode-coupled, and wherein the current loop further comprises a bias transistor coupled between the second PMOS transistor and a bias voltage node and a bias current source coupled between a bias voltage node and a ground node, wherein the bias voltage node is coupled between the first and second branches of the current loop.

An integrated circuit comprising:

• a voltage supply node configured to be coupled to an external voltage source;
• and
• a plurality of power control circuits, wherein each of the plurality of power control circuits includes a control circuit, a power circuit, and an LDO voltage regulator, wherein the LDO voltage regulator of at least one of the plurality of power control circuits includes:
• a current loop comprising a source follower coupled to an output node, the source follower including a first PMOS transistor and a current mirror coupled between a first branch of the current loop and a second branch of the current loop, wherein the source follower is implemented in the second branch, wherein the current loop further comprises a bias current source coupled between the current loop and a ground node and a bias transistor having a drain terminal coupled directly to the current mirror and a source terminal coupled directly to the bias current source, wherein the source terminal of the bias transistor and the bias current source are further coupled to a bias voltage node connecting the first and second branches of the current loop;
• and
• a voltage loop comprising an amplifier circuit having an inverting input coupled to the output node, a non-inverting input coupled to receive a reference voltage, and an amplifier output coupled to a gate terminal of the first PMOS transistor.