Vertical field-effect transistor with uniform bottom spacer

A semiconductor structure, comprising:

• a substrate;
• bottom source/drain regions disposed over the substrate;
• two or more fins disposed over a top surface of the bottom source/drain regions;
• and
• bottom spacers disposed over the top surface of the bottom source/drain layer between the two or more fins, the bottom spacers having a uniform height on sidewalls of the two or more fins;
• wherein the bottom spacers comprise:
• dielectric regions disposed adjacent the sidewalls of the two or more fins and at least partially filling divots in the bottom source/drain regions;
• and
• liner regions disposed adjacent the dielectric regions;
• and
• wherein the two or more fins comprise channels for a vertical field-effect transistor (VFET) device.

An integrated circuit comprising:

• a vertical field-effect transistor (VFET) device comprising:
• a substrate;
• bottom source/drain regions disposed over the substrate;
• two or more fins disposed over a top surface of the bottom source/drain regions, the two or more fins comprising channels for the VFET device;
• and
• bottom spacers disposed over the top surface of the bottom source/drain layer between the two or more fins, the bottom spacers having a uniform height on sidewalls of the two or more fins;
• wherein the bottom spacers comprise:
• dielectric regions disposed adjacent the sidewalls of the two or more fins and at least partially filling divots in the bottom source/drain regions;
• and
• liner regions disposed adjacent the dielectric regions.