Counting circuit including a plurality of latch circuits and image sensing device with the counting circuit

A counting circuit comprising:

• a sampling circuit configured to sample an inverted bit signal, which corresponds to any one of inverted signals of a bit signal and a previous bit signal, as the bit signal in response to a counting target clock signal;
• a first latch circuit configured to latch the bit signal, as which the sampling circuit samples the inverted bit signal corresponding to the inverted signal of the bit signal during a first period, as the previous bit signal at a first time point in response to a first latch control signal, and provide the previous bit signal to the sampling circuit at a third time point in response to a load control signal;
• a second latch circuit configured to latch the bit signal, as which the sampling circuit samples the inverted bit signal corresponding to the inverted signal of the bit signal during a second period, as a first counting bit signal at a second time point in response to a second latch control signal;
• and
• a third latch circuit configured to latch the bit signal, as which the sampling circuit samples the inverted bit signal corresponding to the inverted signal of the previous bit signal during a third period, as a second counting bit signal at a fourth time point in response to a third latch control signal.