Network controller-sideband interface port controller

A network interface controller for providing a connection for a device to a network, the network interface controller comprising a sideband port controller, the sideband port controller for providing a sideband connection between the network and a sideband endpoint circuit that is operative to communicate information with the network via a sideband, the sideband port controller comprising:

• a transmit data route having an input for receiving sideband packets from the sideband endpoint circuit and an output for passing the sideband packets received from the sideband endpoint circuit to the network;
• a packet parser connected to the transmit data route, the packet parser operative to read data from the sideband packets received from the sideband endpoint circuit and further operative to analyze the read data;
• a packet injection register (PIR) that is configured to accept the sideband packets when the PIR has available bandwidth to store the sideband packets;
• a latch configured to be set when an end-of-packet (EOP) marker signals that the PIR has no available bandwidth;
• a packet injection arbiter (PIA) configured to select the sideband packets to be forwarded to an output XS1 buffer, and to prioritize forwarding the sideband packets to an XS2 buffer over forwarding the sideband packets to the output XS1 buffer, wherein both the output XS1 buffer and the XS2 buffer are connected to the transmit data route, wherein the PIA is connected to a leak mechanism that forwards the sideband packets to the network, wherein the output XS1 buffer transmits received sideband packets to a main media access controller (MAC);
• a counter configured to increment when an in-band packet is advanced, along the transmit data route, from the output XS1 buffer to the XS2 buffer and to reset when any sideband packet is advanced from the network interface controller, wherein the PIA is arranged to allow the sideband packet to advance when the counter has reached a certain value;
• a packet engage latch that is set when either the output XS1 buffer or the XS2 buffer is selected to receive either the in-band packet or the sideband packet, wherein the packet engage latch is in the PIA;
• and
• a transfer logic block configured to stop data packets from being transferred by the XS2 buffer and the PIR in response to receiving a signal indicating that the XS1 buffer is full.