Methods of manufacturing inner spacers in a gate-all-around (GAA) FET through multi-layer spacer replacement

A method of manufacturing a semiconductor device, comprising:

• forming a fin structure having a bottom part and a stacked part in which first semiconductor layers and second semiconductor layers are alternately stacked over the bottom part;
• forming a sacrificial gate structure over the fin structure;
• forming a first cover layer over the sacrificial gate structure and a second cover layer over the first cover layer, the second cover layer being made of a different material than the first cover layer;
• forming a source/drain epitaxial layer over the bottom part of the fin structure;
• after the source/drain epitaxial layer is formed, removing the second cover layer, thereby forming a gap between the source/drain epitaxial layer and the first cover layer, from which a part of the fin structure is exposed;
• removing part of the first semiconductor layers in the gap, thereby forming spaces between the second semiconductor layers;
• filling the spaces with a first insulating material, thereby forming insulating spacers,
• wherein the first cover layer remains over the sacrificial gate structure during the filling the spaces with the first insulating material;
• after the insulating spacers are formed, removing the sacrificial gate structure, thereby exposing a part of the fin structure;
• removing the first semiconductor layers from the exposed fin structure, thereby forming channel layers including the second semiconductor layers;
• and
• forming a gate dielectric layer and a gate electrode layer around the channel layers.

A method of manufacturing a semiconductor device, comprising:

• forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked,
• wherein the first semiconductor layers are formed of a first semiconductor material composition and the second semiconductor layers are formed of a second semiconductor material composition, and the first semiconductor material composition and the second semiconductor material composition are different;
• forming a sacrificial gate structure over the fin structure;
• forming a first cover layer over the sacrificial gate structure and a second cover layer over the first cover layer;
• forming a source/drain epitaxial layer on opposing sides of the sacrificial gate structure;
• after the source/drain epitaxial layer is formed, removing the second cover layer, thereby forming a gap between the source/drain epitaxial layer and the first cover layer, from which a part of the fin structure is exposed;
• removing part of the first semiconductor layers in the gap, thereby forming spaces between the second semiconductor layers;
• and
• filling the spaces with a first insulating material,
• wherein the first insulating material is in direct contact with the first semiconductor material composition of the first semiconductor layer and the second semiconductor material composition of the second semiconductor layer.