Partial remainder/divisor table split implementation

A system-on-a-chip (SoC) comprising:

• an instruction circuit configured to issue an instruction to an arithmetic circuit, wherein the instruction is associated with an input value;
• the arithmetic circuit comprising:
• a key selector configured to select a personality key from at least a portion of the input value,
• a sparse look-up table generator is configured to create a sparse look-up table from a partial-remainder lookup table by:
• select, based upon at least a portion of the input value, a column of a partial-remainder look-up table, wherein the partial-remainder look-up table includes a plurality of entries that include a portion of the personality key,
• select, based upon a prior remainder, a row of the partial-remainder look-up table,
• collapse rows having common entries,
• shift a center line by a predefined amount, and
• fold non-negative rows and negative rows to form a folded sparse look-up table;
• a sparse look-up table that is folded, and configured to determine a portion of a result based upon the personality key and a prior remainder,
• an adder configured to compute a current remainder based upon the input value, and the portion of the result, and
• wherein the arithmetic circuit is configured to iteratively compute current remainders and portions of the result until either the current remainder is zero, or a predefined level of precision is reached;
• and
• a memory configured to store the result.