Wafer tap domain die channel circuitry with separate die clocks

An integrated circuit wafer, comprising:

• A. a number N of dies formed on the wafer, where N is greater than 2, each die including:
• i. combinational logic core circuitry;
• ii. a test access port (TAP) domain coupled to the combinational logic core circuitry, the test access port domain having a test data input (TDI) input lead, a test mode select (TMS) input lead, a test clock (TCK) input lead, and a test data output (TDO) output lead;
• iii. scan path circuitry coupled to the combinational logic core circuitry and the test access port domain;
• and
• iv. die channel circuitry having a Data I/O (DIO) bidirectional lead, a clock input (CLK) lead, a TDI output lead coupled to the TDI input lead, a TMS output lead coupled to the TMS input lead, a TCK output lead coupled to the TCK input lead, and a TDO input lead coupled to the TDO output lead, the die channel circuitry including:
• a. a simultaneous bidirectional transceiver (SBT) connected to the DIO bidirectional lead and having an input connected to the TDO input lead, and a serial output lead;
• and
• b. serial input parallel output (SIPO) circuitry having an input connected to the serial output lead of the simultaneous bidirectional transceiver, a clock input connected with the clock input lead, a TDI output connected to the TDI output lead, and a TMS output connected to the TMS output lead;
• and
• B. a wafer clock lead formed on the wafer and coupled to the clock input (CLK) of each die.