Interface chip and built-in self-test method therefor

A built-in self-test method for an interface chip, comprising:

• coupling a transmission terminal of the interface chip back to the interface chip via a reception terminal of the interface chip;
• using a digital code generator of the interface chip to generate a source code;
• using a scrambler of the interface chip to scramble the source code to generate a scrambled code;
• using an encoder of the interface chip to encode the scrambled code to generate an encoded and scrambled code;
• conveying the encoded and scrambled code to an electrical physical layer of the interface chip to be converted to a signal that is provided to the transmission terminal and output from the interface chip and then directly coupled back to the interface chip via the reception terminal and converted to a receiving code by the electrical physical layer;
• using a decoder of the interface chip to decode the receiving code to generate a decoded code;
• using a descrambler of the interface chip to descramble the decoded code to generate a restored code;
• using a code checker of the interface chip to compare the restored code with the source code obtained directly from the digital code generator, without being transmitted and returned back by the transmission terminal, and the reception terminal to determine whether the restored code matches the source code;
• and
• conveying the receiving code from the electrical physical layer to the decoder through a buffer for clock compensation,
• wherein a variety of test patterns are derived by the scrambler corresponding to the source code,
• the digital code generator repeats the generation of a fixed symbol as the source code several times, and inserts a clock compensation symbol between different series of the fixed symbol to be processed by the scrambler, the encoder, and the electrical physical layer, and then output by the interface chip via the transmission terminal and coupled back to the interface chip via the reception terminal and processed by the electrical physical layer, the buffer for clock compensation, the decoder, the descrambler and the code checker;
• and
• the receiving code corresponding to the clock compensation symbol is adjusted in the buffer for clock compensation.

An interface chip, comprising:

• a digital code generator, generating a source code;
• a code checker, receiving a restored code and the source code, wherein the code checker compares the restored code with the source code obtained directly from the digital code generator, without being transmitted and returned back by the transmission terminal, and the reception terminal to determine whether the restored code matches the source code when a transmission terminal of the interface chip is directly coupled back to the interface chip via a reception terminal of the interface chip;
• and
• a buffer for clock compensation, wherein the receiving code from the electrical physical layer is conveyed to the decoder through the buffer for clock compensation,
• wherein:
• the source code is scrambled and encoded and then output from the interface chip via the transmission terminal and coupled back to the interface chip via the reception terminal and then decoded and descrambled to the restored code;
• a variety of test patterns are derived corresponding to the source code by the scrambling the source code;
• the digital code generator repeats the generation of a fixed symbol as the source code several times, and inserts a clock compensation symbol between different series of the fixed symbol to be processed by the scrambler, the encoder, and the electrical physical layer, and then output by the interface chip via the transmission terminal and coupled back to the interface chip via the reception terminal and processed by the electrical physical layer, the buffer for clock compensation, the decoder, the descrambler and the code checker;
• and
• the receiving code corresponding to the clock compensation symbol is adjusted in the buffer for clock compensation.