Test apparatus and testable asynchronous circuit

A test apparatus comprising:

• a first input end, a second input end, a third input end, a fourth input end, a fifth input end, a processing unit, a first output end, and a second output end, wherein
• a) the first input end is connected to a previous circuit under test, and is configured to input a data signal of the previous circuit under test or a test result of a previous circuit under test;
• b) the second input end is connected to a test excitation signal/test result output end of a previous test apparatus, and is configured to input the test excitation signal or the test result output by the previous test apparatus;
• c) the third input end is connected to a clock signal source, and is configured to input a clock signal;
• d) the fourth input end is connected to a selection signal controller, and is configured to input a selection signal;
• and
• e) the fifth input end is connected to a selection signal controller, and is configured to input a selection signal;
• the first output end is connected to a next circuit under test, and is configured to output a data signal or a test excitation signal to the next circuit under test;
• the second output end is connected to a test excitation signal/test result input end of a next test apparatus, and is configured to output the test excitation signal or the test result to the next test apparatus;
• the processing unit is configured to:
• a) when a first selection signal is input at the fifth input end, output, at the first output end, the data signal of the previous circuit under test that is input at the first input end to the next circuit under test;
• or
• b) when a second selection signal is input at the fifth input end and a second selection signal is input at the fourth input end, on a pulse edge of the clock signal that is input at the third input end, output, at the first output end, the test excitation signal that is input at the second input end to the next circuit under test, and output, at the second output end, the test excitation signal that is input at the second input end to the next test apparatus;
• or
• c) when a second selection signal is input at the fifth input end and a first selection signal is input at the fourth input end, on a pulse edge of the clock signal that is input at the third input end, output, at the second output end, the test result of the previous circuit under test that is input at the first input end to the next test apparatus;
• or
• d) when a second selection signal is input at the fifth input end and a second selection signal is input at the fourth input end, on a pulse edge of the clock signal that is input at the third input end, output, at the second output end, the test result that is output by the previous test apparatus and input at the second input end to the next test apparatus;
• a second output end, a third selector and a third output end, wherein, the second output end is connected to the Q output end of the D flip-flop;
• a first input end of the third selector is connected to the first input end of the test apparatus;
• a second input end of the third selector is connected to the third input end of the test apparatus;
• a selection signal end of the third selector is connected to the fifth input end of the test apparatus;
• an output end of the third selector is connected to the third output end of the test apparatus;
• and
• the third selector is configured to, according to the selection signal that is input at the fifth input end of the test apparatus, determine to output the signal that is input at the first input end of the test apparatus or the signal that is input at the third input end of the test apparatus to the third output end of the test apparatus.