Semiconductor device having electrically floating body transistor, semiconductor device having both volatile and non-volatile functionality and method of operating
OwnerYuniarto Widjajainventor
Life of this patent
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Abstract
A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.
Claims17
A semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a plurality of rows and a plurality of columns, each said semiconductor memory cell comprising:
- a substrate;
- a floating body region exposed at a surface of said substrate and configured to store volatile memory;
- a buried layer buried in a bottom portion of said substrate;
- wherein applying a bias to said buried layer results in at least two stable floating body region charge levels;
- a single polysilicon floating gate configured to store nonvolatile data;
- an insulating region insulating said floating body region from said single polysilicon floating gate;
- and
- first and second regions exposed at said surface at locations other than where said floating body region is exposed;
- wherein said floating gate is configured to receive transfer of data stored by the volatile memory;
- and
- wherein said buried layer is commonly connected to at least two of said memory cells.
A semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a plurality of rows and a plurality of columns, each said semiconductor memory cell comprising:
- a substrate;
- a floating body region for storing data as volatile memory, said floating body region having a first conductivity type;
- a buried layer buried in a bottom portion of said substrate;
- wherein applying a bias to said buried layer results in at least two stable floating body region charge levels;
- and
- a single polysilicon floating gate for storing data as non-volatile memory;
- wherein said floating body region stores the data stored as volatile memory independently of said data stored as non-volatile memory, and said single polysilicon floating gate stores said data stored as non-volatile memory independently of said data stored as volatile memory;
- and
- wherein said buried layer is commonly connected to at least two of said memory cells.
Dependencies are inferred from the claim text.