Spur cancellation system for modems

A demodulator, comprising:

• a receiver;
• and
• a direct current removing (DCR) circuit comprising a system of registers configured to bit shift a signal according to one of a plurality of loop gain values, the DCR circuit transitions among:
• an acquisition mode, wherein the DCR circuit operates with a loop gain block having a first loop gain and first accumulation value to identify a plurality of harmonic spurs resulting from a 16 MHz clock frequency oscillator, including a spur at 2480 MHz coinciding with a center frequency of a Bluetooth low energy radio;
• a tracking mode, wherein the DCR circuit operates with the loop gain block having a second loop gain and second accumulation value;
• and
• a holding mode, wherein the DCR circuit freezes a loop gain of the DCR circuit for data demodulation,
• wherein:
• the second loop gain is smaller than the first loop gain;
• the second accumulation value is defined by the first accumulation value multiplied by the first loop gain, divided by the second loop gain;
• each of the first loop gain and second loop gain is constrained to a power of 2;
• a timing of the transition between the acquisition mode and tracking mode is programmable;
• the transition to the holding mode occurs upon completion of synchronization;
• and
• the DCR circuit re-identifies the spurs, beginning with the frozen loop gain, whenever the receiver is cycled from an off power state to an on power state.

A method for demodulating a signal, comprising:

• placing a direct current removing (DCR) circuit into an acquisition mode having a first loop gain and a loop gain block maintains a first accumulation value;
• setting an acquisition mode timer of no more than 4 microseconds;
• identifying a spur in a plurality of harmonic spurs resulting from a 16 MHz clock frequency oscillator, the spur at 2480 MHz coinciding with a center frequency of a Bluetooth low energy radio;
• converting a signal from a first clock domain defined by the clock frequency, to a second clock domain having a lower clock speed than the first clock domain via bit shift by a decimation filter;
• placing the DCR circuit into a tracking mode having a second loop gain and the loop gain block maintains a second accumulation value based on at least one of the acquisition mode timer expiring or identifying the spur;
• and
• re-identifying the spurs whenever a receiver is cycled from an off power state to an on power state,
• wherein:
• the second loop gain is smaller than the first loop gain;
• the second accumulation value is defined by the first accumulation value multiplied by the first loop gain, divided by the second loop gain.