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AssigneeSDRF EURl
InventorsBiagio Bisanti, Eric Duvivier, Lorenzo Carpineto, Stefano Cipriani, Francesco Coppola, Gianni Puccio, Rémi Artinian, Francois Marot, Vanessa Bedero, Lysiane Koechlin
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A multiloop PLL circuit comprising: a first PLL loop comprising a first VCO, a first phase detector having a first input receiving a reference frequency (Fref) and a second input receiving the output of a first programmable divider, which input receives the signal generated by the first VCO and a first loop filter connected between said first phase detector and said first VCO; at least one auxiliary PLL loop comprising a second VCO, a second phase detector, a second (R1) and a third (N1) programmable dividers, and a second loop filter a main loop for generating a desired output frequency Fout comprising a third VCO, a third phase detector, a fourth (Rn) and a fifth (Nn) programmable divider, a main loop filter and a mixer additional possible auxiliary PLL loop each comprising a forth VCO, a forth phase detector, a sixth (Ri) and a seventh (Ni) programmable divider, a third auxiliary loop filter and a mixer whereby the desired output frequency Fout is generated in accordance with the relation: Fout=(N1/R1+ . . . +Nn/Rn)*Fcro where N1 and R1 are the dividing values of the first auxiliary loop and Ni and Ri with i=2 . . . n−1 being the dividing ratios of any possible further auxiliary loop; and Fcro is the frequency generated by VCO, whereby the multiloop circuit is configured with dividing values which optimizes a cost function F.
A multiloop phase locked loop (PLL) circuit comprising, in combination:
A process for generating a stable and accurate output frequency (Fout), comprising the steps of:
Dependencies are inferred from the claim text.