Die sidewall interconnects for 3D chip assemblies

An integrated circuit (IC) chip assembly, comprising:

• a first IC chip;
• and
• a sidewall interconnect trace in contact with a conductive trace that intersects an edge sidewall of the first IC chip, wherein the sidewall interconnect trace is electrically coupled to a second IC chip;
• a first side of the first IC chip includes a plurality of first metal interconnect features bonded to corresponding metal interconnect features of the second IC chip;
• the sidewall interconnect trace extends from the edge sidewall to a second side of the first IC chip;
• and
• the sidewall interconnect trace is electrically coupled through a bond wire to a substrate of the assembly.

An integrated circuit (IC) chip assembly, comprising:

• an IC chip comprising a first conductive trace that intersects an edge sidewall of the IC chip;
• and
• a sidewall interconnect trace in contact with the first conductive trace, wherein:
• the first conductive trace is within a level of interconnect metallization on a first side of the IC chip, and is separated from a second conductive trace that intersects the edge sidewall by a thickness of semiconductor, the second trace within a level of interconnect metallization on a second side of the IC chip;
• and
• the sidewall interconnect trace contacts the second conductive trace, electrically coupling interconnect metallization levels on opposite sides of the IC chip.

A memory chip assembly, comprising:

• a package substrate including a plurality of signal pads;
• a first memory IC die comprising a first interconnect metallization level below a second interconnect metallization level;
• a second memory IC die;
• and
• a sidewall interconnect trace in contact with a conductive trace in the first interconnect metallization level, wherein the conductive trace intersects an edge sidewall of the first die, and the sidewall interconnect trace is electrically coupled to at least one of:
• the first die;
• the second die;
• or one of the signal pads.