Memory device with in-system repair capability
AssigneeRambus Inc.
InventorsFrederick A. Ware, Suresh Rajan, Brent Haukness, Scott C. Best, Wayne F. Ellis
Life of this patent
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Abstract
A memory device is disclosed that includes a row of storage locations to store a data word, and a spare row element. The data word is encoded via an error code for generating error information for correcting X bit errors or detecting Y bit errors, where Y is greater than X. The spare row element has substitute storage locations. The logic is responsive to detected errors to (1) enable correction of a data word based on the error information where there are no more than X bit errors, and (2) substitute the spare row element for a portion of the row where there are at least Y bit errors in the data word.
Claims17
A dynamic random access memory (DRAM) integrated circuit (IC) chip, comprising:
- a memory interface for coupling to an integrated circuit (IC) memory controller chip;
- multiple independent banks, each of the multiple independent banks accessible via a corresponding bank address generated by the IC memory controller chip and including a row of first DRAM storage locations to store a data word, the row including multiple sub-rows, each sub-row separately accessible via a corresponding sub-row address, the data word being encoded via an error code, the error code being used to generate error information, wherein the row includes second DRAM storage locations to store a portion of the error information generated by the error code, wherein the error information is used to correct either X bit errors or detect Y bit errors, where Y is greater than X;
- a spare sub-row element having substitute storage locations;
- logic disposed on the DRAM IC chip, the logic responsive to detected errors in the data word associated with a given one of the multiple sub-rows, the logic to (1) enable correction of the data word based on the error information where there are no more than X bit errors, and (2) substitute the spare sub-row element for the given one of the multiple sub-rows where there are at least Y bit errors in the given one of the multiple sub-rows.
A dynamic random access memory (DRAM) integrated circuit (IC) chip comprising:
- a memory interface for coupling to an integrated circuit (IC) memory controller chip;
- an array of memory units that form plural rows of DRAM storage locations, the DRAM storage locations to store data words that are encoded via an error code, the encoded data words including error information, wherein each of the DRAM storage locations store a portion of the error information generated by the error code, each memory unit including plural normal sub-rows of normal storage locations and a spare sub-row, wherein each of the plural normal sub-rows of DRAM storage locations is separately addressable and comprises an aggregate number of the plural normal sub-rows, each of the plural normal sub-rows having the same sub-row location across all of the memory units;
- and
- repair logic disposed on the DRAM IC chip to detect at least one error in a given one of the plural normal sub-rows based on the error code, and to selectively substitute the given one of the plural normal sub rows with the spare sub-row.
A method of operation in a dynamic random access memory (DRAM) integrated circuit (IC) chip, the method comprising:
- activating a row of DRAM storage cells, the row of DRAM storage cells including a data word that is encoded via an error code, wherein the row includes multiple sub-rows that are accessible via a sub-row address, the row including storage locations to store a portion of the error information generated by the error code, the error code to generate error information used for correcting either X bit errors or detecting Y bit errors in a given one of the multiple sub-rows, and where Y is greater than X;
- determining whether any bit errors exist in the given one of the multiple sub-rows;
- and
- correcting the detected bit errors with logic disposed on the DRAM IC chip by (1) enabling correction of a data word having no more than X bit errors, and (2) substituting a spare sub-row element for the given one of the multiple sub-rows in response to detecting at least Y bit errors in the given one of the multiple sub-rows.
Dependencies are inferred from the claim text.