High speed data synchronization
AssigneeSK hynix Inc.
InventorsGeun Ho Choi, Min Su Park
Life of this patent
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Abstract
According to an embodiment, a semiconductor device may be provided. The semiconductor device may include an internal clock generation circuit configured to generate a plurality of internal clock signals respectively from a plurality of division clock signals. The semiconductor device may include a data input and output (I/O) circuit configured to output input data as output data in synchronization with the plurality of internal clock signals. Each bit of the output data may be outputted in sequential order in synchronization with an internal clock signal from the plurality of internal clock signals.
Claims20
A semiconductor device comprising:
- an internal clock generation circuit configured to generate first to fourth internal clock signals from first to fourth division clock signals;
- and
- a data input and output (I/O) circuit configured to output input data as output data in synchronization with the first to fourth internal clock signals,
- wherein the first internal clock signal is generated after the fourth internal clock signal is generated, the second internal clock signal is generated after the first internal clock signal is generated, the third internal clock signal is generated after the second internal clock signal is generated, and the fourth internal clock signal is generated after the third internal clock signal is generated.
A semiconductor device comprising:
- a control circuit configured to generate first to fourth enablement signals which are set to have an enablement period corresponding to a multiple of a cycle of first to fourth pre-clock signals based on a pulse signal;
- an internal clock generation circuit configured to generate first to fourth internal clock signals from first to fourth division clock signals based on the first to fourth enablement signals;
- and
- a data input and output (I/O) circuit configured to output input data as output data in synchronization with the first to fourth internal clock signals,
- wherein the first internal clock signal is generated during the enablement period of the first enablement signal, the second internal clock signal is generated during the enablement period of the second enablement signal, the third internal clock signal is generated during the enablement period of the third enablement signal, and the fourth internal clock signal is generated during the enablement period of the fourth enablement signal.
Dependencies are inferred from the claim text.