Scatter reduction instruction

A processor comprising:

• a register array comprising a first element that stores a first register value that identifies a first memory location, a second element that stores a second register value that identifies a second memory location, and a third element that stores a third register value that identifies a third memory location;
• a decoder circuit to:
• receive a single instruction multiple data (SIMD) instruction from an application, the SIMD instruction identifying the register array and an array of input values comprising at least a first input value, a second input value, and a third input value;
• and
• decode the SIMD instruction;
• and
• a processor core to:
• perform an operation on the first input value and the first register value to obtain a first operation value, and wherein the first register value is stored at a first location of the register array;
• perform the operation on the second input value and the second register value to obtain a second operation value, and wherein the second register value is stored at a second register array location of the register array;
• and
• perform the operation the third input value and the third register value, and wherein the second register value is stored at a third location of the register array,
• wherein the operation on the first, second, and third input values are performed in parallel;
• associate the first operation value with the first location;
• associate the second operation value with the second location;
• associate a third operation value with the third location;
• determine that the first register value and the second register value are the same value, wherein the third register value is different than the first register value and the second register value;
• perform a horizontal add operation on the first operation value and the second operation value to obtain a result value;
• write the result value to the second memory location, wherein the second memory location and the first memory location are the same when the first register value and the second register value are the same;
• and
• write the third operation value to the third memory location.

A method comprising:

• performing, by a processor, an operation on a first set of variables to obtain a first operation value;
• performing, by the processor, the operation on a second set of variables to obtain a second operation value;
• performing, by the processor, the operation on a third set of variables to obtain a third operation value, wherein the operation on the first set of variables, the operation on second set of variables, and the operation on third set of variables is performed in parallel;
• associating, by the processor, the first operation value with a first location at a register array;
• associating, by the processor, the second operation value with a second location at the register array;
• associating, by the processor, the third operation value with a third location at the register array;
• determining, by the processor, that a register value at the first location and a register value at the second location identify a same memory location;
• performing, by the processor, a horizontal add operation on the first operation value and the second operation value to obtain a result value;
• and
• writing, by the processor, the result value to the same memory location identified by the second location and the third operation value to a third memory location identified by a register value at the third location.