Digital phase locked loop frequency estimation
AssigneeIntel IP Corporation
InventorsElan Banin, Roy Amel, Ran Shimon, Ashoke Ravi, Nati Dinur
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Abstract
A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a Voltage Controlled Oscillator (VCO) signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and least-squares estimate a frequency based on the quantized phase values and the wraparound phase.
Claims23
A Digital Phase Locked Loop (DPLL), comprising:
- a Time-to-Digital Converter (TDC) configured to generate quantized phase values of a Voltage Controlled Oscillator (VCO) signal;
- and
- a frequency estimation circuit configured to receive the quantized phase values, determine a wraparound phase of the quantized phase values, and least-squares estimate a frequency based on the quantized phase values and the wraparound phase.
A method of operating a Digital Phase Locked Loop (DPLL), comprising:
- generating, by a Time-to-Digital Converter (TDC), quantized phase values of a Voltage Controlled Oscillator (VCO) signal;
- determining, by a frequency estimation circuit, a wraparound phase of the quantized phase values;
- and
- least-squares estimating, by the frequency estimation circuit, a frequency based on the quantized phase values and the wraparound phase.
A method of fast locking a Digital Phase Locked Loop (DPLL), comprising:
- setting a constant tuning voltage of a Voltage Controlled Oscillator (VCO) using an open control loop;
- least-squares estimating a frequency based on quantized phase values and a wraparound phase of a VCO signal;
- determining a tuning voltage offset of the VCO based on the estimated frequency;
- and
- updating the tuning voltage of the VCO to compensate for the tuning voltage offset.
Dependencies are inferred from the claim text.