US 10,170,174 B1Granted

Apparatus and methods for refreshing memory

AssigneeMicron Technology, Inc.

InventorsYutaka Ito, Yuan He

Life of this patent

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Abstract

Apparatuses for executing row hammer refresh are described. An example apparatus includes: memory banks, each memory bank of the memory banks includes: a latch that stores a row address; and a time based sampling circuit. The time based sampling circuit includes: a sampling timing generator that provides a timing signal of sampling a row address; and a plurality of bank sampling circuits, wherein each bank sampling circuit of the bank sampling circuits is included in a corresponding memory bank of the memory banks and provides a sampling signal to the latch in the corresponding memory bank responsive to the timing signal of sampling the row address; and an interval measurement circuit that receives an oscillation signal, measures an interval of a row hammer refresh execution based on a cycle of the oscillation signal, and further provides a steal rate timing signal for adjusting a steal rate to the sampling timing generator.

Claims20

Dependent claims

An apparatus comprising:

a row hammer control circuit configured to provide a row hammer control signal that is in an active state at variable intervals, the row hammer control signal including a first active state, a second active state and a third active state, the second active state being between the first and third active states, each of the first, second and third active states configured to cause a row hammer refresh operation;
a latch circuit configured to temporarily store a row address on which the row hammer refresh operation is performed;
a first counter circuit configured to count a number of pulses of a clock signal as a first count from the first active state to the second active state of the row hammer control signals and further configured to provide the first count;
and
a second counter circuit configured to start counting a number of pulses of the clock signal as a second count responsive, at least in part, to the third active state of the row hammer control signal and further configured to assert a timing signal when the second count is equal to or greater than zero and less than the first count value,
wherein the latch circuit is further configured to update the row address, responsive, at least in part, to the timing signal.

3 more elements

An apparatus comprising:

a plurality of memory banks, wherein each memory bank of the plurality of memory banks is associated with a latch configured to store a row address for row hammer refresh;
and
a time based sampling circuit including:
a sampling timing generator configured to provide a timing signal of sampling a row address;
a plurality of bank sampling circuits, wherein each bank sampling circuit of the plurality of bank sampling circuits is associated with a corresponding memory bank of the plurality of memory banks, wherein each bank sampling circuit is configured to provide a sampling signal to the latch of the corresponding memory bank responsive to the timing signal of sampling the row address;
and
an interval measurement circuit configured to receive an oscillation signal, configured to measure an interval of a row hammer refresh execution based on a cycle of the oscillation signal, and further configured to provide a steal rate timing signal for adjusting a steal rate to the sampling timing generator,
wherein the sampling timing generator is further configured to provide the timing signal of sampling the row address, responsive, at least in part, to the steal rate timing signal, and
wherein the latch of the corresponding memory bank is configured to store the row address, responsive, at least in part, to the timing signal of sampling the row address.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/796,340Filed 27 Oct 2017
Granted: 1 Jan 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G11C 11/40622
Management or control of the refreshing or charge-regeneration cycles: partial refresh of memory arrays
G11C 11/40615
Management or control of the refreshing or charge-regeneration cycles: internal triggering or timing of refresh, e.g. hidden refresh, self…
G11C 11/4076
For memory cells of the field-effect type: timing circuits
G11C 11/4087
Address circuits: address decoders, e.g. bit - or word line decoders; Multiple line decoders