Driver circuit for transmitter

A driver circuit, comprising:

• a first inverter, connected between a first supply voltage and ground, that receives an input data signal and generates an inverted version of the input data signal, the first inverter comprising:
• a first transistor having a source connected to the first supply voltage and a gate for receiving the input data signal;
• and
• a second transistor having a source connected to the ground, a gate connected to the gate of the first transistor, and a drain connected to a drain of the first transistor for outputting the inverted version of the input data signal;
• a bias-control circuit, connected between a second supply voltage and the first inverter, that receives the inverted version of the input data signal, a bias signal, and an enable signal and generates a level-shifted data signal at a first node of the driver circuit based on the inverted version of the input data signal, the bias signal, the enable signal, and the second supply voltage, wherein the bias-control circuit reduces a difference between voltage levels of the second supply voltage and the inverted version of the input data signal, and wherein the bias-control circuit comprises:
• a third transistor having a source for receiving the bias signal and a gate for receiving an inverted version of the enable signal;
• a fourth transistor having a source connected to the second supply voltage, a gate for receiving the enable signal, and a drain connected to a drain of the third transistor;
• a first resistor that is connected between the drain of the fourth transistor and the first node;
• and
• a capacitor that is connected between the drain of the second transistor and the first node;
• and
• a second inverter, connected between the second supply voltage and the ground, that is connected to the first node and the first inverter for receiving the level-shifted data signal and the inverted version of the input data signal, respectively, and generating an output data signal at a second node of the driver circuit, the second inverter comprising:
• a fifth transistor having a source connected to the second supply voltage, a gate connected to the first node for receiving the level-shifted data signal, and a drain connected to the second node;
• and
• a sixth transistor having a source connected to the ground, a gate connected to the drain of the second transistor, and a drain connected to the second node for generating the output data signal at the second node.

A serializer-deserializer (SerDes), comprising:

• a transmitter that outputs an output data signal, the transmitter comprising:
• a control circuit, connected to first and second supply voltages and ground, that generates a first input data signal and a bias signal;
• and
• a transmitter-driver circuit, connected to the control circuit, that includes a first driver circuit, receives the bias signal and the first input data signal, and outputs the output data signal, wherein the first driver circuit comprises:
• a first inverter, connected between the first supply voltage and the ground, that receives the first input data signal and generates an inverted version of the first input data signal;
• a first bias-control circuit, connected between a second supply voltage and the first inverter, that receives the inverted version of the first input data signal and the bias signal and generates a first level-shifted data signal based on the inverted version of the first input data signal, the bias signal, and the second supply voltage, wherein the first bias-control circuit reduces a difference between voltage levels of the second supply voltage and the inverted version of the first input data signal, and a voltage level of the bias signal is equal to a difference between a voltage level of the second supply voltage and half of a voltage level of the first supply voltage;
• and
• a second inverter, connected between the second supply voltage and the ground, that is connected to the first bias-control circuit and the first inverter for receiving the first level-shifted data signal and the inverted version of the first input data signal, respectively, and generating the output data signal.