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US 10,163,907 B2Granted
Method of maintaining the state of semiconductor memory having electrically floating body transistor
AssigneeZeno Semiconductor, Inc.
InventorsYuniarto Widjaja, Zvi Or-Bach
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Abstract
Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.
Claims22
An integrated circuit comprising:
- an array of semiconductor memory cells formed in a semiconductor substrate having at least one surface, the array comprising:
- said semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes:
- a transistor comprising a source region, a floating body region, a drain region, and a gate;
- a first bipolar device having a first floating base region, a first emitter, and a first collector;
- and
- a second bipolar device having a second floating base region, a second emitter, and a second collector,
- wherein said first floating base region and said second floating base region are common to said floating body region;
- wherein said first collector is common to said second collector;
- wherein at least one of said first bipolar device or second bipolar device maintains a state of said memory cell;
- wherein said transistor is usable to access said memory cell;
- a first control circuit configured to perform a holding operation on said array;
- and
- a second control circuit configured to access a selected memory cell and perform a read or write operation on said selected memory cell.
10 more elements
An integrated circuit comprising:
- an array of semiconductor memory cells formed in a semiconductor substrate having at least one surface, the array comprising:
- said semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes:
- a transistor comprising a source region, a floating body region, a drain region, and a gate;
- a first bipolar device having a first floating base region, a first emitter, and a first collector;
- and
- a second bipolar device having a second floating base region, a second emitter, and a second collector,
- wherein said first floating base region and said second floating base region are common to said floating body region;
- wherein said first collector is common to said second collector;
- wherein at least one of said first bipolar device or second bipolar device maintains a state of said memory cell;
- wherein said transistor is usable to access said memory cell;
- a first control circuit configured to access a selected memory cell and perform a read or write operation on said selected memory cell;
- and
- a second control circuit configured to provide electrical signals to perform a holding operation on said array, wherein said electrical signals are applied to a terminal not used for memory address selection.
10 more elements
Dependencies are inferred from the claim text.