Cell architecture with intrinsic decoupling capacitor

A method of operation of an integrated circuit (IC), the IC including at least a first IC portion and a second IC portion on a first side of the first IC portion, the method comprising:

• providing a first voltage in a first set of metal x (Mx) layer power interconnects, an array of cells being in the first IC portion, the array of cells including the first set of Mx layer power interconnects coupled to a first voltage source and extending adjacent to a p-type metal oxide semiconductor (MOS) (pMOS) active region in a first direction across the array of cells, the array of cells further including a first set of Mx layer interconnects extending adjacent to the pMOS active region in the first direction across the array of cells;
• providing a second voltage in a second set of Mx layer power interconnects, the array of cells including the second set of Mx layer power interconnects coupled to a second voltage source less than the first voltage source and extending adjacent to an n-type MOS (nMOS) active region in the first direction across the array of cells, the array of cells further including a second set of Mx layer interconnects extending adjacent to the nMOS active region in the first direction across the array of cells, a first set of endcap cells being in the second IC portion, wherein the first set of Mx layer power interconnects, the first set of Mx layer interconnects, the second set of Mx layer power interconnects, and the second set of Mx layer interconnects further extend across the first set of endcap cells;
• providing the first voltage at the second set of Mx layer interconnects, the first set of endcap cells including a first set of metal x+1 (Mx+1) layer interconnects extending in a second direction orthogonal to the first direction, the first set of Mx+1 layer interconnects being coupled to the first set of Mx layer power interconnects and to the second set of Mx layer interconnects to provide the first voltage source at the second set of Mx layer interconnects;
• and
• providing the second voltage at the first set of Mx layer interconnects, the first set of endcap cells including a second set of Mx+1 layer interconnects extending in the second direction, the second set of Mx+1 layer interconnects being coupled to the second set of Mx layer power interconnects and to the first set of Mx layer interconnects to provide the second voltage source at the first set of Mx layer interconnects,
• wherein the first set of Mx layer power interconnects and the first set of Mx layer interconnects function as a first set of decoupling capacitors, and the second set of Mx layer power interconnects and the second set of Mx layer interconnects function as a second set of decoupling capacitors.

An integrated circuit (IC), the IC including at least a first IC portion and a second IC portion on a first side of the first IC portion, the IC comprising:

• means for providing a first voltage in a first set of metal x (Mx) layer power interconnects, an array of cells being in the first IC portion, the array of cells including the first set of Mx layer power interconnects coupled to a first voltage source and extending adjacent to a p-type metal oxide semiconductor (MOS) (pMOS) active region in a first direction across the array of cells, the array of cells further including a first set of Mx layer interconnects extending adjacent to the pMOS active region in the first direction across the array of cells;
• means for providing a second voltage in a second set of Mx layer power interconnects, the array of cells including the second set of Mx layer power interconnects coupled to a second voltage source less than the first voltage source and extending adjacent to an n-type MOS (nMOS) active region in the first direction across the array of cells, the array of cells further including a second set of Mx layer interconnects extending adjacent to the nMOS active region in the first direction across the array of cells, a first set of endcap cells being in the second IC portion, wherein the first set of Mx layer power interconnects, the first set of Mx layer interconnects, the second set of Mx layer power interconnects, and the second set of Mx layer interconnects further extend across the first set of endcap cells;
• means for providing the first voltage at the second set of Mx layer interconnects, the first set of endcap cells including a first set of metal x+1 (Mx+1) layer interconnects extending in a second direction orthogonal to the first direction, the first set of Mx+1 layer interconnects being coupled to the first set of Mx layer power interconnects and to the second set of Mx layer interconnects to provide the first voltage source at the second set of Mx layer interconnects;
• and
• means for providing the second voltage at the first set of Mx layer interconnects, the first set of endcap cells including a second set of Mx+1 layer interconnects extending in the second direction, the second set of Mx+1 layer interconnects being coupled to the second set of Mx layer power interconnects and to the first set of Mx layer interconnects to provide the second voltage source at the first set of Mx layer interconnects,
• wherein the first set of Mx layer power interconnects and the first set of Mx layer interconnects function as a first set of decoupling capacitors, and the second set of Mx layer power interconnects and the second set of Mx layer interconnects function as a second set of decoupling capacitors.