Two-port SRAM connection structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon Jhy Liaw
Life of this patent
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Abstract
A static random access memory (SRAM) device is provided in accordance with some embodiments. The SRAM device comprises a plurality of two-port SRAM arrays, which comprise a plurality of two-port SRAM cells. Each two-port SRAM cell comprises a write port portion, a read port portion, a first plurality of metal lines located in a first metal layer, a second plurality of metal lines located in a second metal layer, a third plurality of metal lines located in a third metal layer a plurality of edge cells, a plurality of well strap cells, and a plurality of jumper structures. Each jumper structure comprises first, second, and third metal landing pads located in the second metal layer and electrically connecting metal lines of the first and third metal layers.
Claims20
A device comprising:
- a peripheral logic region that includes a first plurality of conductor lines located in a first conductor layer;
- a memory region that includes:
- a second plurality of conductor lines, wherein the second plurality of conductor lines is located in the first conductor layer;
- a third plurality of conductor lines, wherein the third plurality of conductor lines is located in a third conductor layer;
- and
- a jumper structure comprising:
- a first landing pad located in a second conductor layer and electrically connected to a first line of the second plurality of conductor lines and a second line of the third plurality of conductor lines;
- a second landing pad located in the second conductor layer and electrically connected to a third line of the second plurality of conductor lines and a fourth line of the third plurality of conductor lines;
- and
- a third landing pad located in the second conductor layer and electrically connected to a fifth line of the second plurality of conductor lines and a sixth line of the first plurality of conductor lines.
A device comprising:
- a peripheral logic region that includes a first plurality of conductor lines in a first layer, wherein lines of the first plurality of conductor lines extend in a first direction and are arranged at a first pitch in a second direction perpendicular to the first direction;
- a memory region that includes a second plurality of conductor lines in the first layer, wherein lines of the second plurality of conductor lines extend in the first direction and are arranged at a second pitch in the second direction that is different from the first pitch;
- a jumper electrically coupling a first line of the first plurality of conductor lines to a second line of the second plurality of conductor lines, wherein the jumper includes:
- a landing pad in a second layer that extends over the first line and the second line;
- a first via to electrically couple the first line to the landing pad;
- and
- a second via to electrically couple the second line to the landing pad.
A device comprising:
- a peripheral logic region that includes a first plurality of conductor lines in a first layer, wherein lines of the first plurality of conductor lines extend in a first direction and are arranged at a first pitch;
- a memory region that includes a first sub array and a second sub array, wherein:
- the first sub array includes a second plurality of conductor lines in the first layer;
- and
- the lines of the second plurality of conductor lines extend in the first direction and are arranged at a second pitch that is different from the first pitch;
- a third plurality of conductor lines in a third conductor layer that extend between the first sub array and the second sub array;
- and
- a jumper structure that includes:
- a first landing pad located in a second conductor layer and electrically connected to a first line of the second plurality of conductor lines and a second line of the third plurality of conductor lines;
- a second landing pad located in the second conductor layer and electrically connected to a third line of the second plurality of conductor lines and a fourth line of the third plurality of conductor lines;
- and
- a third landing pad located in the second conductor layer and electrically connected to a fifth line of the second plurality of conductor lines and a sixth line of the first plurality of conductor lines.
Dependencies are inferred from the claim text.