Periphery fill and localized capacitance
AssigneeMicron Technology, Inc.
InventorsChristopher John Kawamura, Scott James Derner
Life of this patent
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Abstract
Methods, systems, and devices for periphery fill and localized capacitance are described. A memory array may be fabricated with certain containers connected to provide capacitance rather than to operate as memory cells. For example, a memory cell having one or two transistors, or other switching components, and one capacitor, such as a ferroelectric or dielectric capacitor, may be electrically isolated from one or more containers sharing a common access line, and the isolated containers may be used as capacitors. The capacitors may be used for filtering in some examples. Or the capacitance may be used to boost or regulate voltage in, for example, support circuitry.
Claims17
An electronic memory apparatus, comprising:
- a memory cell that comprises a selector device, a second selector device, and a memory element formed in a container type common to an array that comprises the memory cell, wherein the memory element is coupled with a first segment of a first access line via the selector device, and wherein the memory element is coupled with a first segment of a second access line via the second selector device;
- and
- a capacitor formed in the container type common to the array and coupled with a second segment of the first access line, wherein the capacitor is coupled with a second segment of the second access line and electrically isolated from the memory cell.
A method, comprising:
- accessing a memory cell from an array of memory cells that is in electronic communication with a first segment of a first access line and support circuitry;
- and
- capacitively coupling a node in the support circuitry with at least one capacitor that is in electronic communication with a second segment of the first access line while accessing the memory cell, wherein the memory cell and the at least one capacitor are electrically isolated from one another, and wherein the at least one capacitor and the memory cell comprise a same container type.
An electronic memory apparatus comprising:
- an array of memory cells in electronic communication with a first segment of a first access line;
- a plurality of capacitors in electronic communication with a second segment of the first access line, wherein each of the plurality of capacitors is in electronic communication with the second segment of the first access line via a switching component;
- and
- a controller in electronic communication with each of the plurality of capacitors, wherein the controller is operable to:
- access a memory cell from the array of memory cells that is in electronic communication with the first segment of the first access line and support circuitry;
- and
- capacitively couple a node in the support circuitry with at least one capacitor that is in electronic communication with the second segment of the first access line while accessing the memory cell, wherein the memory cell and the at least one capacitor are electrically isolated from one another, and where the at least one capacitor comprises and each of the memory cells comprise a same container type.
Dependencies are inferred from the claim text.