Data receiver and controller for DDR memory
AssigneeNovatek Microelectronics Corp.
InventorsPo-Yao Ko, Chien-Chung Chen, Hsu-Yu Huang, Chun-Po Huang
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Abstract
A data receiver for a double data rate (DDR) memory includes a first stage circuit and a second stage circuit. The first stage circuit is deployed for receiving a single-ended signal from the DDR memory and converting the single-ended signal into a pair of differential signals. The second stage circuit, coupled to the first stage circuit, is deployed for receiving the differential signals from the first stage circuit and converting the differential signals into an output signal. Both of the first stage circuit and the second stage circuit are implemented in a core voltage domain.
Claims21
A data receiver for a double data rate (DDR) memory, comprising:
- a first stage circuit, for receiving a single-ended signal from the DDR memory and converting the single-ended signal into a pair of differential signals;
- and
- a second stage circuit, coupled to the first stage circuit, for receiving the differential signals from the first stage circuit and converting the differential signals into an output signal;
- wherein the first stage circuit and the second stage circuit are implemented in a core voltage domain, and the single-ended signal received by the first stage circuit exceeds the core voltage domain.
A controller for a double data rate (DDR) memory, comprising:
- a data transmitter;
- and
- a data receiver, comprising:
- a first stage circuit, for receiving a single-ended signal from the DDR memory and converting the single-ended signal into a pair of differential signals;
- and
- a second stage circuit, coupled to the first stage circuit, for receiving the differential signals from the first stage circuit and converting the differential signals into an output signal;
- wherein the first stage circuit and the second stage circuit are implemented in a core voltage domain, and the single-ended signal received by the first stage circuit exceeds the core voltage domain.
A data receiver for a double data rate (DDR) memory, comprising:
- a first stage circuit, configured to receive a single-ended signal from the DDR memory and convert the single-ended signal into a pair of differential signals;
- and
- a second stage circuit, coupled to the first stage circuit and configured to receive the differential signals from the first stage circuit and convert the differential signals into an output signal;
- wherein the first stage circuit is configured to operate in a core voltage domain, and the single-ended signal exceeds the core voltage domain.
Dependencies are inferred from the claim text.