Double affine mapped S-box hardware accelerator
AssigneeIntel Corporation
InventorsSudhir K. Satpathy, Sanu K. Mathew, Vinodh Gopal, Kirk S. Yap
Life of this patent
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Abstract
A processing system includes a memory and a cryptographic accelerator module operatively coupled to the memory, the cryptographic accelerator module employed to implement a byte substitute operation by performing: a first mapped affine transformation of an input bit sequence to produce a first intermediate bit sequence, an inverse transformation of the first intermediate bit sequence to produce a second intermediate bit sequence, and a second mapped affine transformation of the second intermediate bit sequence to produce an output bit sequence.
Claims14
A processing system for performing a cryptographic operation comprising a byte substitution operation, the processing system comprising:
- a memory device;
- a cryptographic accelerator module operatively coupled to the memory device, the cryptographic accelerator module to implement the byte substitute operation by performing:
- a first mapped affine transformation of an input bit sequence to produce a first intermediate bit sequence, wherein the first mapped affine transformation is represented by a first mapped affine transformation matrix produced by multiplying a first mapping matrix and a first transformation matrix,
- an inverse transformation of the first intermediate bit sequence to produce a second intermediate bit sequence, and
- a second mapped affine transformation of the second intermediate bit sequence to produce an output bit sequence.
A method, comprising:
- performing, by a cryptographic accelerator module, a byte substitution operation comprising:
- a first mapped affine transformation of an input bit sequence to produce a first intermediate bit sequence, wherein the first mapped affine transformation is represented by a first mapped affine transformation matrix produced by multiplying a first mapping matrix and a first transformation matrix,
- an inverse transformation of the first intermediate bit sequence to produce a second intermediate bit sequence, and
- a second mapped affine transformation of the second intermediate bit sequence to produce an output bit sequence;
- and
- performing a cryptographic operation using the output bit sequence.
Dependencies are inferred from the claim text.