Digital phase locked loop and operating method of digital phase locked loop

A digital phase locked loop comprising:

• a digital phase detector configured to output phase information based on a phase of a reference signal having a reference frequency and a phase of a feedback signal having a first frequency such that the phase information indicates whether the phase of the feedback signal is advanced or delayed with respect to the phase of the reference signal;
• a digital loop filter configured to perform first low pass filtering on the phase information in a frequency domain, and the digital loop filter configured to output a result of the first low pass filtering as a digital code;
• a digital controlled oscillator configured to output an oscillation signal having a second frequency, and the digital controlled oscillator configured to adjust a frequency of the oscillation signal depending on the digital code;
• a first divider configured to perform a first division to divide the second frequency of the oscillation signal based on a first division value, and the first divider configured to output a result of the first division as a division signal having a third frequency;
• a second divider configured to perform a second division to divide the second frequency of the oscillation signal based on a second division value, and the second divider configured to output a result of the second division as an output signal having a final frequency;
• a dithering block configured to perform dithering, in cycles of the division signal, on the first division value based on a pattern;
• a digital phase domain filter configured to perform second low pass filtering on the division signal in a phase domain, and the digital phase domain filter configured to output the result of the second low pass filtering as a filtered signal;
• and
• a third divider configured to perform a third division to divide a frequency of the filtered signal based on a third division value, and the third divider configured to output a result of the third division as the feedback signal.

A method of operating a digital phase locked loop, the method comprising:

• generating phase information based on a phase of a reference signal having a reference frequency and a phase of a feedback signal having a first frequency such that the phase information indicates whether the phase of the feedback signal is advanced or delayed with respect to the phase of the reference signal,
• accumulating, at a digital loop filter of the digital phase locked loop, the phase information to generate a digital code;
• outputting, at a digital controlled oscillator of the digital phase locked loop, an oscillation signal based on the digital code;
• performing, at a first divider of the digital phase locked loop, dithering on a first division value and dividing a frequency of the oscillation signal based on the first division value to output a division signal;
• and
• performing, at a digital phase domain filter of the digital phase locked loop, low pass filtering on the division signal to generate a next feedback signal of a next clock cycle.