Power supply glitch detector

A power supply glitch detector comprising:

• a first sensing node AC coupled to a power supply node on which positive voltage glitches having a magnitude of at least Vglitch+ are to be detected;
• a first sensing inverter having an input and an output, the input coupled to the first sensing node, the first sensing inverter having a trip voltage Vtrip+ below which the output of the first sensing inverter is at a voltage representing a logic high state and above which the output of the first sensing inverter is at a voltage representing a logic low state;
• a first user-settable voltage biasing circuit coupled to the first sensing node to maintain the input of the first sensing inverter at a settable bias voltage Vbias+, wherein Vbias+ is chosen such that both conditions (Vbias+<Vtrip+) and (Vbias++Vglitch+>Vtrip+) are always true;
• a second sensing node AC coupled to a power supply node on which negative voltage glitches having a magnitude of at least Vglitch− are to be detected;
• a second sensing inverter having an input and an output, the input coupled to the second sensing node, the second sensing inverter having a trip voltage Vtrip− below which the output of the second sensing inverter is at a voltage representing a logic high state and above which the output of the second sensing inverter is at a voltage representing a logic low state;
• a second user-settable voltage biasing circuit coupled to the second sensing node to maintain the input of the second sensing inverter at a settable bias voltage Vbias−, wherein Vbias− is chosen such that both conditions (Vbia−s>Vtrip−) and (Vbias−−Vglitch−<Vtrip−) are always true.