US 10,153,768 B1Granted

Integrated circuitry and methods for reducing leakage current

AssigneeNXP USA, Inc.

InventorsChristopher James Micielli, Srikanth Jagannathan, Hector Sanchez, Kumar Abhishek

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Abstract

Input/output circuitry includes a first PMOS device and a first NMOS device having first current electrodes are connected to each other and a pad. First selection circuitry, when the I/O circuitry is disabled, provides a first supply voltage to a control electrode and an N-well of the first PMOS device when the pad voltage is between the first and second supply voltages and to directly provide the pad voltage to the control electrode and the N-well of the first PMOS device when the pad voltage is greater than the first supply voltage. Similarly, second selection circuitry, when the I/O circuitry is disabled, provides a second supply voltage or directly provides the pad voltage to a control electrode and a P-well of the first NMOS device depending on whether the pad voltage is between the first and second supply voltages or less than the second supply voltage, respectively.

Claims20

Dependent claims

An integrated circuit, comprising:

a pad configured to receive a pad voltage;
input/output (I/O) circuitry coupled to the pad and having a first P-type Metal-Oxide-Semiconductor (PMOS) device and a first N-type Metal-Oxide-Semiconductor (NMOS) device, wherein a first current electrode of the first PMOS device is connected to a first current electrode of the first NMOS and to the pad;
a first voltage supply node configured to receive a first supply voltage;
a second voltage supply node configured to receive a second supply voltage different from the first supply voltage;
first selection circuitry configured to, when the I/O circuitry is disabled, provide the first supply voltage to a control electrode of the first PMOS device and an N-well of the first PMOS device when the pad voltage is lower than the first supply voltage and to directly provide the pad voltage to the control electrode of the first PMOS device and the N-well of the first PMOS device when the pad voltage is greater than the first supply voltage;
and
second selection circuitry configured to, when the I/O circuitry is disabled, provide the second supply voltage to a control electrode of the first NMOS device and a P-well of the first NMOS device when the pad voltage is higher than the second supply voltage and to directly provide the pad voltage to the control electrode of the first NMOS device and the P-well of the first NMOS device when the pad voltage is less than the second supply voltage.

4 more elements

An integrated circuit, comprising:

a pad configured to receive a pad voltage;
input/output circuitry coupled to the pad and having a first P-type Metal-Oxide-Semiconductor (PMOS) device and a first N-type Metal-Oxide-Semiconductor (NMOS) device, wherein a first current electrode of the first PMOS device is connected to a first current electrode of the first NMOS and to the pad;
a first voltage supply node configured to receive a first supply voltage;
a second voltage supply node configured to receive a second supply voltage different from the first supply voltage;
first selection circuitry coupled to the first voltage supply node, the second voltage supply node, and the pad;
second selection circuitry coupled to the first voltage supply node, the second voltage supply node, and the pad;
first comparison circuitry coupled to the first voltage supply node and the pad and having a first output configured to, when the I/O circuitry is disabled, provide a first comparison result between the pad voltage and the first supply voltage to the first selection circuitry;
and
second comparison circuitry coupled to the second voltage supply node and the pad and a first output configured to, when the I/O circuitry is disabled, provide a second comparison result between the pad voltage and the second supply voltage to the second selection circuitry,
wherein the first selection circuitry includes:
a second PMOS device having a first current electrode coupled to the pad, a control electrode coupled to the first output of the first comparison circuitry, and a second current electrode coupled to the N-well of the first PMOS device;
a third PMOS device having a first current electrode coupled to the first voltage supply node, a control electrode coupled to a second output of the first comparison circuitry, and a second current electrode;
and
a fourth PMOS device having a first current electrode coupled to the second current electrode of the third PMOS device, a control electrode coupled to a third output of the first comparison circuitry, and a second current electrode coupled to the N-well of the first PMOS device, and
wherein the second selection circuitry includes:
a second NMOS device having a first current electrode coupled to the pad, a control electrode coupled to the first output of the second comparison circuitry, and a second current electrode;
a third NMOS device having a first current electrode coupled to the second current electrode of the second NMOS device, a control electrode coupled to the first output of the second comparison circuitry, a second current electrode coupled to the control electrode of the first NMOS device, and a body electrode coupled to the P-well of the first NMOS device;
a fourth NMOS device having a first current electrode coupled to the second voltage supply node, a control electrode coupled to a second output of the second comparison circuitry, and a second current electrode;
and
a fifth NMOS device having a first current electrode coupled to a second current electrode of the fourth NMOS device, a control electrode coupled to a third output of the second comparison circuitry, and a body electrode coupled to the P-well of the first NMOS device.

17 more elements

An integrated circuit, comprising:

a pad configured to receive a pad voltage;
input/output circuitry coupled to the pad and having a first P-type Metal-Oxide-Semiconductor (PMOS) device and a first N-type Metal-Oxide-Semiconductor (NMOS) device, wherein a first current electrode of the first PMOS device is connected to a first current electrode of the first NMOS and to the pad;
a first voltage supply node configured to receive a first supply voltage;
a second voltage supply node configured to receive a second supply voltage different from the first supply voltage;
first selection circuitry configured to, when the I/O buffer is disabled, provide the first supply voltage to a control electrode of the first PMOS device and an N-well of the first PMOS device when the pad voltage is between the first and second supply voltage and to directly provide the pad voltage to the control electrode of the first PMOS device and the N-well of the first PMOS device when the pad voltage is greater than the first supply voltage;
second selection circuitry configured to provide the second supply voltage to a control electrode of the first NMOS device and a P-well of the first NMOS device when the pad voltage is between the first and second supply voltage and to directly provide the pad voltage to the control electrode of the first NMOS device and the P-well of the first NMOS device when the pad voltage is less than the second supply voltage;
first comparison circuitry comprising:
a first voltage divider having:
a second PMOS device having a first current electrode coupled to the first voltage supply node, a second current electrode, and a control electrode coupled to the second current electrode of the second PMOS device, and
a plurality of PMOS devices coupled in series between the second current electrode of the second PMOS device and the second voltage supply node, wherein the first voltage divider is configured to provide a divided voltage based on the first supply voltage at the second current electrode of the second PMOS device when the I/O circuitry is disabled;
and
a third PMOS device have a first current electrode coupled to the pad, a control electrode coupled to the second current electrode of the second PMOS device, and a second current electrode configured to provide the third output of the first comparison circuitry when the I/O circuitry is disabled;
and
second comparison circuitry comprising:
a second voltage divider having:
a second NMOS device having a first current electrode, a second current electrode coupled to the second voltage supply node, and a control electrode coupled to the second current electrode of the second NMOS device, and
a plurality of NMOS devices coupled in series between the first voltage supply node and the first current electrode of the second NMOS device, wherein the voltage divider is configured to provide a divided voltage based on the first supply voltage at the first current electrode of the second NMOS device;
and
a third NMOS device have a first current electrode configured to provide the third output of the second comparison circuitry when the I/O circuitry is disabled, a control electrode coupled to the first current electrode of the second NMOS device, and a second current electrode coupled to the pad.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/908,255Filed 28 Feb 2018
Granted: 11 Dec 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H03K 17/6872
The output circuit comprising more than one controlled field-effect transistor: using complementary field-effect transistors
H03K 17/162
In field-effect transistor switches: without feedback from the output circuit to the control circuit
H10D 89/811
For devices having insulated gate electrodes, e.g. for IGFETs or IGBTs: using FETs as protective elements
H03K 2217/0018
Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00: special modifications or…