Methods and structures for a split gate memory cell structure
AssigneeNXP USA, Inc.
InventorsCheong Min Hong, Sung-Taeg Kang
Life of this patent
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Abstract
A method of forming a split gate memory cell structure using a substrate includes forming a gate stack comprising a select gate and a dielectric portion overlying the select gate. A charge storage layer is formed over the substrate including over the gate stack. A first sidewall spacer of conductive material is formed along a first sidewall of the gate stack extending past a top of the select gate. A second sidewall spacer of dielectric material is formed along the first sidewall on the first sidewall spacer. A portion of the first sidewall spacer is silicided using the second sidewall spacer as a mask whereby silicide does not extend to the charge storage layer.
Claims19
A split gate memory cell structure, comprising:
- a gate stack over a semiconductor substrate, wherein the gate stack has a conductive portion with a top surface and a dielectric portion having a bottom surface on the top surface of the conductive portion, the gate stack having a first sidewall along a first side of the conductive portion and a first side of the dielectric portion;
- a charge storage layer along a first portion of the first sidewall and extending over a first portion of the substrate;
- a first sidewall spacer on the charge storage layer along the first portion of the first sidewall and extending over the first portion of the substrate, wherein the first sidewall spacer comprises conductive material and wherein the first portion of the first sidewall includes the first side of the conductive portion and a first portion of the first side of the dielectric portion;
- a second sidewall spacer on a top portion of the first sidewall spacer and along the first sidewall above the first sidewall spacer, wherein the second sidewall spacer comprises dielectric material, and wherein a portion of the second sidewall spacer is directly above the first sidewall spacer;
- and
- a silicide layer on a top surface of the first sidewall spacer;
- wherein the silicide layer adjoins the second sidewall spacer and does not contact the charge storage layer below the dielectric portion.
A split gate memory cell structure, comprising:
- a gate stack over the semiconductor substrate, wherein the gate stack has a conductive portion with a top surface and a dielectric portion having a bottom surface on the top surface of the conductive portion, the gate stack having a first sidewall along a side of the conductive portion and a side of the dielectric portion;
- a charge storage layer over the substrate including over the gate stack and along the first sidewall;
- a first conductive spacer (26) over the charge storage layer and along the first sidewall, wherein a top of the first conductive spacer is above the top surface of the conductive portion and below the top of the dielectric portion;
- a first sidewall (40) spacer extending from a lower surface of the first conductive spacer to a first height below the top of the first conductive spacer;
- a second sidewall (38) spacer along the first sidewall between the top of the first conductive spacer and the top surface of the dielectric portion, wherein a portion of the second sidewall spacer is directly above the conductive spacer;
- and
- silicide layer (46) on a top surface of the first conductive spacer between the first sidewall spacer and the second sidewall spacer.
Dependencies are inferred from the claim text.