Fan out wafer level package type semiconductor package and package on package type semiconductor package including the same

A fan out wafer level package type semiconductor package, comprising:

• a substrate having a first surface and a second surface opposite to the first surface, wherein the substrate comprises:
• a plurality of base layers:
• first connection pads on the first surface and second connection pads on the second surface;
• a plurality of conductive vias penetrating the respective ones of the plurality of base layers to electrically connect each first connection pad to a respective second connection pad;
• and
• a cavity penetrating the plurality of base layers and spaced apart from the plurality of conductive vias, the first connection pads and the second connection pads;
• a semiconductor chip in the cavity and spaced apart from an inner sidewall of the cavity, wherein the semiconductor chip includes a plurality of pads including a first pad on an active surface of the semiconductor chip;
• a redistribution structure on the first surface of the substrate and the active surface of the semiconductor chip;
• a first cover layer covering the redistribution structure;
• and
• a second cover layer covering an inactive surface of the semiconductor chip and the second surface of the substrate,
• wherein the redistribution structure comprises:
• a first sub-insulating interlayer on the first surface of the substrate and on the active surface of the semiconductor chip;
• at least one second sub-insulating interlayer on the first sub-insulating interlayer;
• a first via layer penetrating the first sub-insulating interlayer;
• a second via layer penetrating each second sub-insulating interlayer of the at least one second sub-insulating interlayer, respectively, and
• wherein the first cover layer, the second cover layer and the first sub-insulating interlayer are formed of a same material.

A semiconductor package, comprising:

• a redistribution structure including a plurality of insulating interlayers, a first surface, and a second surface opposite the first surface, wherein:
• first pads at the first surface are connected to external package connection terminals, and
• each insulating interlayer includes a plurality of conductive vias passing therethrough, each conductive via connected to a respective conductive via of another insulating interlayer and connected to a respective first pad;
• a first semiconductor chip and a substrate disposed on the second surface of the redistribution structure, wherein the first semiconductor chip is disposed in a cavity of the substrate and has a first surface facing the redistribution structure and a second surface opposite the first surface;
• a first cover layer covering the first surface of the redistribution structure;
• a second cover layer covering the second surface of first semiconductor chip;
• a first sub-insulating layer, which is one of the insulating interlayers of the redistribution structure, covering the first surface of the first semiconductor chip;
• and
• a second semiconductor chip formed above the first semiconductor chip and on the substrate, wherein
• the first cover layer, second cover layer, and first sub-insulating layer each have the same coefficient of thermal expansion.