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US 10,148,469 B2Granted
Apparatus and method for cancelling pre-cursor inter-symbol-interference
AssigneeIntel Corporation
InventorsMor M. Cohen, Yaniv Hadar, Ehud U. Shoor
Life of this patent
Estimating the term…
Abstract
An apparatus is provided which comprises: a data slicer to receive first data sampled by a data clock; an edge slicer to receive second data sampled by an edge clock; and a Least Mean Square (LMS) circuitry coupled to the data and edge slicers, wherein the LSM circuitry is to generate a code to adjust a phase of one of data clock and/or edge clock relative to one another.
Claims20
An apparatus comprising:
- a data slicer to receive first data sampled by a data clock;
- an edge slicer to receive second data sampled by an edge clock;
- a Least Mean Square (LMS) circuitry coupled to the data and edge slicers, wherein the LMS circuitry is to generate a code to adjust a phase of one of the data clock or edge clock relative to one another;
- a phase generator coupled to the LMS circuitry, wherein the phase generator is to receive the code and to adjust the phase of one of the data clock or edge clock relative to one another, and wherein the phase generator is to generate a first data clock and a first edge clock;
- and
- a current mode logic to CMOS (CML2CMOS) converter coupled to the phase generator.
3 more elements
A method comprising:
- receiving input data;
- disabling a gain control mechanism which adjusts gain of an amplifier that amplifies the received input data;
- enabling a least mean square (LMS) circuitry;
- determining a step candidate associated with the LMS circuitry to generate a phase offset code;
- enabling the gain control mechanism;
- and
- applying the phase offset code to adjust a phase of one of a data clock and/or an edge clock relative to one another.
4 more elements
A system comprising:
- a memory;
- a processor coupled to the memory, the processor comprising a receiver which includes:
- a data slicer to receive first data sampled by a data clock;
- an edge slicer to receive second data sampled by an edge clock;
- a Least Mean Square (LMS) circuitry coupled to the data and edge slicers, wherein the LMS circuitry is to generate a code to adjust a phase of one of the data clock or edge clock relative to one another;
- a phase generator coupled to the LMS circuitry, wherein the phase generator is to receive the code and to adjust the phase of one of the data clock or edge clock relative to one another, and wherein the phase generator is to generate a first data clock and a first edge clock;
- and
- a finite state machine (FSM) to pause adjustment to an automatic gain control (AGC) circuitry before the phase of one of the data clock or the edge clock is adjusted relative to one another;
- and
- a wireless interface to allow the processor to communicate with another device.
7 more elements
Dependencies are inferred from the claim text.