Low noise amplifier circuit

A semiconductor circuit, comprising:

• an input block comprising a first chopper adapted for providing a chopped input voltage signal indicative of a voltage signal to be amplified;
• at least one amplifier having an inverting input port and a non-inverting input port and an output port,
• and wherein either an output port of the first chopper is connected to the non-inverting input port of the at least one amplifier, or the non-inverting input port of the at least one amplifier is connected to a constant or a common voltage and the output port of the first chopper is connected to the inverting input port of the at least one amplifier via at least one intermediate component adapted for converting the chopped input voltage signal into a chopped current signal;
• a second chopper having an input port and an output port, the input port being connected to the output port of the at least one amplifier;
• a third chopper having an input port and an output port, the output port being connected to the inverting input port of the at least one amplifier;
• at least one integration capacitor connected between the output port of the second chopper and the input port of the third chopper;
• a sample-and-hold circuit connected to the output port of the at least one amplifier or to the output port of the second chopper, directly or indirectly, the sample-and-hold circuit being configured to provide a zero order hold voltage signal;
• a proportional feedback network having an input port connected directly or indirectly to the output port of the sample-and-hold circuit, and being adapted for providing a proportional feedback signal, and having an output port connected directly or indirectly to the inverting input port of the at least one amplifier;
• wherein a voltage of the at least one integration capacitor provides a continuous-time voltage signal being an amplified version of the voltage signal to be amplified;
• and wherein the values of the proportional feedback network are chosen such that an amplitude ratio of the continuous-time signal and the voltage signal to be amplified is at least 2.0;
• and wherein the value of the at least one integration capacitor is chosen such that, for a chopped input signal equal to zero, a charge stored on the integrating capacitor at the beginning of a sample period is linearly removed during one single sampling period of the sampling signal, in such a way that the charge is completely removed at the end of the single sampling period;
• and wherein each chopper is adapted to be operated at a chopping frequency, and the sample-and-hold-block is adapted to be operated at a sampling frequency, wherein the sampling frequency is equal to the chopping frequency or to an integer multiple larger than zero thereof.