US 10,141,953 B2Granted

Low-density parity-check apparatus and matrix trapping set breaking method

AssigneeVIA Technologies, Inc.

InventorsYing Yu Tai, Jiangli Zhu

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Abstract

A low-density parity-check (LDPC) apparatus and a matrix trapping set breaking method are provided. The LDPC apparatus includes a logarithm likelihood ratio (LLR) mapping circuit, a variable node (VN) calculation circuit, an adjustment circuit, a check nodes (CN) calculation circuit and a controller. The LLR mapping circuit converts an original codeword into a LLR vector. The VN calculation circuit calculates original V2C information by using the LLR vector and C2V information. The adjustment circuit adjusts the original V2C information to get adjusted V2C information in accordance with a factor. The CN calculation circuit calculates the C2V information by using the adjusted V2C information, and provides the C2V information to the VN calculation circuit. The controller determines whether to adjust the factor. When LDPC iteration operation falls into matrix trap set, the controller decides to adjust the factor so that the iteration operation breaks away from the matrix trap set.

Claims17

Dependent claims

A low-density parity-check (LDPC) apparatus, configured to perform an iteration operation to decode an original codeword, comprising:

a log likelihood ratio (LLR) mapping circuit, configured to convert the original codeword into a LLR vector according to a mapping relationship;
a variable node (VN) calculation circuit, coupled to the LLR mapping circuit for receiving the LLR vector, and configured to calculate at least one original variable-node to check-node (V2C) information from at least one VN to at least one check node (CN) by using the LLR vector and at least one check-node to variable-node (C2V) information;
an adjustment circuit, coupled to the VN calculation circuit to receive the original V2C information, and configured to adjust the original V2C information to obtain at least one adjusted V2C information according to at least one factor, wherein the factor is multiplied to the original V2C information;
a check node calculation circuit, coupled to the adjustment circuit to receive the adjusted V2C information, and configured to calculate the at least one C2V information from the CN to the VN by using the adjusted V2C information, and providing the at least one C2V information to the VN calculation circuit;
and
a controller, coupled to the adjustment circuit, and configured to determine whether to adjust the factor, wherein when the iteration operation falls into a matrix trapping set, the controller decides to adjust the factor to break the iteration operation away from the matrix trapping set.

3 more elements

A matrix trapping set breaking method, configured to make an iteration operation executed by a low-density parity-check apparatus to break away from a matrix trapping set, the matrix trapping set breaking method comprising:

converting an original codeword into a log likelihood ratio (LLR) vector according to a mapping relationship;
calculating at least one original variable-node to check-node (V2C) information from at least one variable node (VN) to at least one check node (CN) by using the LLR vector and at least one check-node to variable-node (C2V) information;
adjusting the original V2C information to obtain at least one adjusted V2C information according to at least one factor, wherein the factor is multiplied to the original V2C information;
calculating the at least one C2V information from the CN to the VN by using the adjusted V2C information;
and
determining whether to adjust the factor, wherein when the iteration operation falls into a matrix trapping set, it is determined to adjust the factor to break the iteration operation away from the matrix trapping set.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/379,450Filed 14 Dec 2016
Published: US 2018/0167086 A114 Jun 2018
Granted: 27 Nov 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

H03M 13/255
Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded…: with…
G11C 29/00
Checking stores for correct operation
G11C 29/028
Detection or location of defective auxiliary circuits, e.g. defective refresh counters: with adaption or trimming of parameters
G11C 29/42
Response verification devices: using error correcting codes [ECC] or parity check