Systems and methods for maintaining refresh operations of memory banks using a shared
AssigneeMicron Technology, Inc.
InventorJoosang Lee
Life of this patent
Estimating the term…
Abstract
A memory device includes memory banks that each have multiple rows with row addresses. The memory device also includes a counter that stores and increments a first row address of a first row of a first set of memory banks to a second row address of a second row of the first set of memory banks in response to a first refresh operation when the memory device is operating in a first mode. The memory device further includes circuitry that blocks incrementing the second row address to a third row address of a third row of the first set of memory banks when the memory device transitions from the first mode to a second mode and the first refresh operation is not paired with a second refresh operation that is performed when the memory device is operating in the first mode.
Claims7
A memory device comprising:
- a plurality of memory banks, wherein each memory bank of the plurality of memory banks comprises a plurality of rows, wherein each row of the plurality of rows comprises a row address;
- a counter configured to store and increment a first row address of a first row of a first set of memory banks of the plurality of memory banks to a second row address of a second row of the first set of memory banks in response to a first refresh operation when the memory device is operating in a first mode;
- and
- circuitry configured to block incrementing the second row address to a third row address of a third row of the first set of memory banks when the memory device transitions from the first mode to a second mode and the first refresh operation is not paired with a second refresh operation that is performed when the memory device is operating in the first mode.
Dependencies are inferred from the claim text.