Computing and summing up multiple products in a single multiplier

A multiplier for computing and summing up multiple products comprises:

• a multiplier circuit that receives, during a first clock cycle, a first number and a second number and responsively creates during a second clock cycle, first partial products based on a multiplication of the first number and the second number;
• a reduction circuit that reduces, during a third clock cycle, the first partial products to create an intermediate result having a first sum value and a first carry value, wherein the reduction circuit outputs the intermediate result as input to the reduction circuit;
• wherein the multiplier circuit receives, during the second clock cycle, a third number and a fourth number and responsively creates, during the third clock cycle, second partial products based on a multiplication of the third number and the fourth number;
• wherein the reduction circuit, during a fourth clock cycle, adds the intermediate result and the second partial products of the third number and the fourth number to create a second sum value and a second carry value;
• and
• an adder circuit that adds the second sum value and the second carry value to create a result.

A multiplier for computing and summing up multiple products comprises:

• a Booth multiplier circuit that receives, during a first clock cycle, a first number and a second number and responsively creates, during a second clock cycle, first partial products based on a multiplication of the first number and the second number;
• a reduction circuit that reduces, during a third clock cycle, the first partial products to create an intermediate result which includes a first sum value and a first carry value, wherein the Booth multiplier circuit includes logic to count and remove carry bits added by the Booth Multiplier during creation of the partial products, wherein the reduction circuit also receives a fifth number during the first clock cycle and wherein the reduction circuit creates the intermediate result based on adding the fifth number to the first partial products;
• wherein the Booth multiplier circuit receives, during the second clock cycle, the intermediate result, a third number and a fourth number and responsively creates, during the third clock cycle, second partial products based on a multiplication of the third number and the fourth number;
• wherein the reduction circuit adds, during a fourth clock cycle, the intermediate result, the first sum value and the first carry value, to the second partial products of the third number and the fourth number to create a reduction tree and reduces the reduction tree to a two-level tree resulting in a second sum value and a second carry value;
• wherein the reduction circuit also receives a sixth number during the second clock cycle and wherein the reduction circuit includes the sixth number in the reduction of the reduction tree to the two-level tree;
• an adder circuit that adds the second sum value and the second carry value to create a result.