Tight pitch vertical transistor EEPROM

A memory device comprising:

• a first conductivity type semiconductor device in a first region of a substrate and a second conductivity type semiconductor device in a second region of the substrate;
• a first source/drain region for each of the first and second conductivity type semiconductor devices, each of the first source/drain regions positioned on the substrate;
• a common floating gate structure in simultaneous electrical communication to a first vertically orientated channel region for the first conductivity type semiconductor device, and a second vertically orientated channel region for the second conductivity type semiconductor device;
• and
• a commonly via contacted second source/drain region present on an end of the first and second vertically orientated channel regions that is opposite the first source/drain region for each of the first and second conductivity type semiconductor devices.

A method of forming a memory device comprising:

• forming a first conductivity type vertically orientated semiconductor device in a first region of a substrate;
• forming a second conductivity type vertically orientated semiconductor device in a second region of the substrate;
• and
• forming a common floating gate structure in simultaneous electrical communication with a first fin structure of the first conductivity type vertically orientated semiconductor device and a second fin structure of the second conductivity type vertically orientated semiconductor device.