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US 10,134,837 B1Granted
Porous silicon post processing
AssigneeQUALCOMM Incorporated
InventorsStephen Alan Fanelli, Richard Hammond
Life of this patent
Estimating the term…
Abstract
A semiconductor on insulator (SOI) device may include a semiconductor handle substrate. The semiconductor hand may include a porous semiconductor layer, and an etch stop layer proximate the porous semiconductor layer. The SOI may also include an insulator layer on the etch stop layer. The SOI may further include a device semiconductor layer on the insulator layer.
Claims13
A semiconductor on insulator (SOI) device, comprising:
- a semiconductor handle substrate comprising a porous semiconductor layer, and an etch stop layer proximate the porous semiconductor layer;
- an insulator layer on the etch stop layer;
- a bulk semiconductor layer between the insulator layer and the etch stop layer;
- and
- a device semiconductor layer on the insulator layer.
2 more elements
A semiconductor on insulator (SOI) device, comprising:
- an insulator layer having a backside surface on a semiconductor handle substrate;
- a device semiconductor layer on a front-side surface of the insulator layer;
- and
- the semiconductor handle substrate including an etch stop layer proximate the insulator layer and a bulk semiconductor layer between the insulator layer and the etch stop layer, the semiconductor handle substrate comprising means for reducing radio frequency (RF) harmonics contacting the etch stop layer.
1 more element
Dependencies are inferred from the claim text.