Structure and method to mitigate soldering offset for wafer-level chip scale package (WLCSP) applications

A microelectromechanical systems (MEMS) package, comprising:

• an integrated circuit comprising a semiconductor substrate having one or more semiconductor devices and an underlying inter-level dielectric (ILD) layer comprising a plurality of metal interconnect layers;
• a MEMS structure bonded to the ILD layer;
• a cap substrate bonded to the MEMS structure through a bond ring and a bond pad arranged on an uppermost surface of the cap substrate, wherein the bond ring and the bond pad are metallic, wherein the cap substrate has recesses including a pad recess and a ring recess, wherein the pad recess is arranged around the bond pad in a continuous, closed path, wherein the ring recess is arranged around the pad recess, along the bond ring, wherein the pad recess is independent of the ring recess, and wherein the uppermost surface is continuous from the pad recess to the ring recess;
• and
• a through substrate via (TSV) arranged within the cap substrate, wherein the TSV extends through the cap substrate from the bond pad and is separated from the pad recess by a region of the cap substrate;
• wherein the pad recess and the ring recess extend into the uppermost surface of the cap substrate, wherein the ring recess has a ring recess sidewall and the bond ring has a bond ring sidewall, and wherein the ring recess sidewall and the bond ring sidewall are collinear and vertically separated by the uppermost surface of the cap substrate.

A microelectromechanical systems (MEMS) package, comprising:

• an integrated circuit (IC) comprising a semiconductor substrate, a dielectric layer, and metallization layers, wherein the dielectric layer is under the semiconductor substrate, and wherein the metallization layers are stacked within the dielectric layer;
• a MEMS structure under and bonded to the IC at an interface between the dielectric layer and the MEMS structure;
• a cavity between the MEMS structure and the dielectric layer;
• a capping substrate under and bonded to the MEMS structure through an uppermost surface of the capping substrate;
• a pair of bond pads stacked between the capping substrate and the MEMS structure;
• a pair of bond rings stacked between the capping substrate and the MEMS structure, wherein the bond rings laterally enclose the bond pads, and wherein the pair of bond rings and the pair of bond pads are metallic;
• a first through via extending from contact with a metallization layer of the IC, through the MEMS structure, to contact with a top one of the bond pads;
• and
• a second through via extending from contact with a bottom one of the bond pads, through the capping substrate, to a bottom surface of the capping substrate;
• wherein the capping substrate comprises a pad recess laterally enclosing one of the bond pads, and extending vertically into the uppermost surface of the capping substrate, wherein the bottom one of the bond pads has a sidewall aligned with a sidewall of the pad recess that is defined by the capping substrate, and wherein the second through via is separated from the pad recess by a region of the capping substrate.