Method for operating single-poly non-volatile memory cell

A method for operating a single-poly non-volatile memory (NVM) cell, wherein the single-poly NVM cell comprises a PMOS select transistor and a PMOS floating gate transistor serially connected to the PMOS select transistor on an N well, wherein the PMOS floating gate transistor comprises a floating gate and a floating gate extension, wherein the floating gate extension is capacitively coupled to an erase gate (EG) region, the method comprising:

• erasing the single-poly NVM cell by applying a bit line voltage to a P+ drain doping region of the floating gate transistor, applying an erase line voltage to the EG region, and applying an N well voltage to the N well;
• wherein the bit line voltage is equal to 0V, the erase line voltage is equal to a positive voltage that is high relative to the bit line voltage;
• and
• wherein the N well voltage is greater than 0V and is in a range between a first drain-to-source saturation voltage VDS-Sat1 and a second drain-to-source saturation voltage VDS-Sat2, wherein the first drain-to-source saturation voltage VDS-Sat1 is an upper limit voltage level to ensure that pinchoff does not occur at two ends of a P channel under the floating gate at the beginning of the erasing operation, while the second drain-to-source saturation voltage VDS-Sat2 is a lower limit voltage level to ensure that pinchoff occurs at two ends of the P channel when the floating gate is in an erased state.