# US 10,122,883 B2 · Image processing apparatus including circuit configuration and method of controlling the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,122,883 B2 - Document ID: US10122883B2 - Status: Granted - Kind: B2 - Application number: 15/119,803 - Filed: 2015-03-31 - Published: 2017-03-02 - Granted: 2018-11-06 - Earliest claimed: 2014-04-08 - Assignees: Canon Kabushiki Kaisha - Applicants: Canon Kabushiki Kaisha - Inventors: Naohiro Yamamoto - Web page: https://patentgrep.com/patent/US10122883B2 ## CPC - H04N 1/0097: {Storage of instructions or parameters, e.g. customised instructions or different parameters for different user IDs} - G06F 3/1204: {resulting in reduced user or operator actions, e.g. presetting, automatic actions, using hardware token storing data} - G06F 3/1205: {resulting in increased flexibility in print job configuration, e.g. job settings, print requirements, job tickets} - G06F 3/1243: {Variable data printing, e.g. document forms, templates, labels, coupons, advertisements, logos, watermarks, transactional printing, fixed content versioning} - G06F 3/1248: {by printer language recognition, e.g. PDL, PCL, PDF} - G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining - H03K 19/17748: Structural details of configuration resources - H03K 19/17756: for partial configuration or partial reconfiguration - H03K 19/17758: for speeding up configuration or reconfiguration - H03K 19/1776: for memories - H04N 1/32122: {in a separate device, e.g. in a memory or on a display separate from image data} - H04N 2201/0094: Multifunctional device, i.e. a device capable of all of reading, reproducing, copying, facsimile transception, file transception - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract An image processing apparatus specifies a difference between a circuit configuration for processing an accepted job and a circuit configuration configured in a reconfiguration circuit, and based on the difference, selects a functional block to be reconfigured in the reconfiguration circuit, and reconfigures the reconfiguration circuit by reading configuration data from storage unit. ## Claims ### Claim 1 An image processing apparatus, comprising: a partially reconfigurable device on which logic circuitry providing one or more image processing functions can be created and which can replace only a part of the logic circuitry with another logic circuitry; at least one processor which functions as: an accepting unit configured to accept an image processing job which is executed using predetermined image processing functions provided by logic circuitry created on the partially reconfigurable device; a reconfiguration unit configured to cause the partially reconfigurable device to create, on the partially reconfigurable device, new logic circuitry providing at least one image processing function which is included in the predetermined image processing functions necessary for executing the accepted job and is not provided by current logic circuitry being on the partially reconfigurable device, with a part of the current logic circuitry which provides another image processing function included in the predetermined image processing functions kept on the partially reconfigurable device; and an execution unit configured to execute the accepted image processing job using both (i) the new logic circuitry which has been created on the partially reconfigurable device and provides the at least one image processing function and (ii) the part of the current logic circuitry which has been kept on the partially reconfigurable device and provide the another image processing function. ### Claim 2 (depends on 1) The image processing apparatus according to claim 1, wherein the at least one processor further functions as a determination unit configured to determine whether or not there is a constraint condition for when the partially reconfigurable device is reconfigured, wherein the reconfiguration unit, in accordance with the constraint condition determined by the determination unit, determines configuration data to use for a reconfiguration. ### Claim 3 (depends on 2) The image processing apparatus according to claim 2, wherein the constraint condition is a condition related to at least one of a circuit scale of the reconfiguration circuit, and a rewrite count. ### Claim 4 (depends on 3) The image processing apparatus according to claim 3, wherein the reconfiguration unit determines the configuration data to use for the reconfiguration in accordance with a processing format of data used in a functional block included in the circuit configuration for processing the job. ### Claim 5 (depends on 1) The image processing apparatus according to claim 1, wherein the at least one processor further functions as a selection unit configured to select the at least one image processing function, in accordance with a difference between the predetermined image processing functions necessary for executing the accepted job and one or more image processing functions provided by the current logic circuitry being on the partially reconfigurable device, wherein the difference includes a difference of a processing format of image data handled in each image processing function. ### Claim 6 (depends on 5) The image processing apparatus according to claim 5, wherein the processing format is a line processing format for handling image data in a line form, a rectangle processing format for handling image data in a rectangular form, or a linear processing format for handling compressed image data. ### Claim 7 (depends on 1) The image processing apparatus according to claim 1, further comprising: a storage for storing circuit configuration data predicted for an initial job that is executed after a power supply activation or after a return from sleep, and the reconfiguration unit, after the power supply activation or after the return from sleep, reconfigures the partially reconfigurable device by reading the predicted configuration data from the storage prior to accepting a job. ### Claim 8 (depends on 1) The image processing apparatus according to claim 1, further comprising a storage storing a plurality of pieces of circuit configuration data, the plurality of pieces of circuit configuration data corresponding respectively to different image processing functions, and wherein the reconfiguration unit is further configured to identify the at least one image processing function, and wherein the partially reconfigurable device obtains, from among the plurality pieces of circuit configuration data, at least one piece of circuit configuration data corresponding to the at least one image processing function identified by the reconfiguration unit and create the new logic circuitry based on the obtained piece of circuit configuration data. ### Claim 9 (depends on 1) The image processing apparatus according to claim 1, wherein the circuit configuration data is data that is reconfigurable in finer processing units than the functional blocks. ### Claim 10 (depends on 1) The image processing apparatus according to claim 1, wherein the partially reconfigurable device does not create, for executing the accepted image processing job, logic circuitry which provides the another image processing function on the partially reconfigurable device. ### Claim 11 An image processing method comprising: at least one processor which functions as: accepting an image processing job which is executed using predetermined image processing functions provided by logic circuitry created on a partially reconfigurable device, wherein the partially reconfigurable device on which logic circuitry providing one or more image processing functions can be created and which can replace only a part of the logic circuitry with another logic circuitry; making, on the partially reconfigurable device, new logic circuitry providing at least one image processing function which is included in the predetermined image processing functions necessary for executing the accepted job and is not provided by current logic circuitry being on the partially reconfigurable device, with a part of the current logic circuitry which provides another image processing function included in the predetermined image processing functions kept on the partially reconfigurable device; and executing the accepted image processing job using both (i) the new logic circuitry which has been created on the partially reconfigurable device and provides the at least one image processing function and (ii) the part of the current logic circuitry which has been kept on the partially reconfigurable device and provide the another image processing function. ### Claim 12 (depends on 11) The image processing method according to claim 11, further comprising: selecting the at least one image processing function, in accordance with a difference between the predetermined image processing functions necessary for executing the accepted job and one or more image processing functions provided by the current logic circuitry being on the partially reconfigurable device, wherein the difference includes a difference of a processing format of image data handled in each image processing function. ### Claim 13 (depends on 12) The image processing method according to claim 12, wherein the processing format is a line processing format for handling image data in a line form, a rectangle processing format for handling image data in a rectangular form, or a linear processing format for handling compressed image data. ### Claim 14 (depends on 11) The image processing method according to claim 11, further comprising avoiding making, for executing the accepted image processing job, logic circuitry which provides the another image processing function on the partially reconfigurable device. ### Claim 15 An image processing apparatus comprising: a partially reconfigurable device on which logic circuitry providing an image processing function can be created with another logic circuitry left on the partially reconfigurable device; one or more controllers which: executes a first image processing job using logic circuitry created on the partially reconfigurable device; accepts a second image processing job; controls the partially reconfigurable device to newly create, on the partially reconfigurable device, logic circuitry providing an image processing function which is required in the second image processing job and is not required in the first image processing job, with a common logic circuitry providing an image processing function commonly required in both of the first image processing job and the accepted second image processing job left on the partially reconfigurable device; and executes the second image processing job using the common logic circuitry left on the partially reconfigurable device and the logic circuitry newly created on the partially reconfigurable device. ### Claim 16 (depends on 15) The image processing apparatus according to claim 15, wherein the one or more controllers perform the control after executing the first image processing job. ### Claim 17 (depends on 15) The image processing apparatus according to claim 15, wherein the common logic circuitry is a part of logic circuitry providing an image processing function required in the first image processing job. ### Claim 18 (depends on 15) The image processing apparatus according to claim 15, wherein the common logic circuitry is used in both the first image processing job and the second image processing job. ### Claim 19 A data processing method using a partially reconfigurable device on which logic circuitry providing a data processing function can be created with another logic circuitry left on the partially reconfigurable device, the data processing method comprising: executing a first data processing job using logic circuitry created on the partially reconfigurable device; accepting a second data processing job; controls the partially reconfigurable device to newly create, on the partially reconfigurable device, logic circuitry providing an data processing function which is required in the second data processing job and is not required in the first data processing job, with a common logic circuitry providing a data processing function commonly required in both of the first data processing job and the accepted second data processing job left on the partially reconfigurable device; and executing the second data processing job using the common logic circuitry left on the partially reconfigurable device and the logic circuitry newly created on the partially reconfigurable device. ### Claim 20 (depends on 19) The data processing method according to claim 19, wherein the newly creating of logic circuitry is performed after executing the first data processing job. ### Claim 21 (depends on 19) The data processing method according to claim 19, wherein the common logic circuitry is a part of logic circuitry providing a data processing function required in the first data processing job. ### Claim 22 (depends on 19) The data processing method according to claim 19, wherein the common logic circuitry is used in both the first data processing job and the second data processing job.