# US 10,122,691 B2 · Receiving apparatus and packet processing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,122,691 B2 - Document ID: US10122691B2 - Status: Granted - Kind: B2 - Application number: 15/203,445 - Filed: 2016-07-06 - Published: 2017-06-22 - Granted: 2018-11-06 - Earliest claimed: 2015-12-18 - Assignees: Realtek Semiconductor Corp. - Applicants: Realtek Semiconductor Corp. - Inventors: Chia-Hung Lin; Chang-Shiuan Yang; Yi-Huei Lei; Chun-Hao Lin - Web page: https://patentgrep.com/patent/US10122691B2 ## CPC - H04L 63/0428: {wherein the data content is protected, e.g. by encrypting or encapsulating the payload} - G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)} - G06F 12/1408: {by using cryptography (for digital transmission H04L9/00)} - H04L 63/0435: {wherein the sending and receiving network entities apply symmetric encryption, i.e. same key used for encryption and decryption (cryptographic mechanisms or cryptographic arrangements for symmetric key encryption H04L9/06)} - H04L 69/12: Protocol engines - H04L 69/164: Adaptation or special uses of UDP protocol - H04L 69/22: Parsing or analysis of headers - H04L 69/26: {Special purpose or proprietary protocols or architectures (network applications for proprietary or special purpose networking environments H04L67/12)} - G06F 2212/1052: Security improvement - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract The present disclosure provides a receiving apparatus for preprocessing at least one segment data packet to a data packet. The receiving apparatus includes a packet parser, a data memory, a decrypt engine, a transmission engine, a header processing unit and a controller. The packet parser fetches segment-packet-header information from a segment packet header of each segment data packet. The decrypt engine decrypts an encrypted data of each segment data packet to obtain a segment payload and a QUIC private header including sequence information. The transmission engine transmits the segment payload to a specific location of a system memory. The header processing unit calculates packet information and updates the segment packet header stored in the data memory to generate a packet header. The controller controls the transmission engine based on the sequence information to output the packet header to the system memory for generating the data packet. ## Claims ### Claim 1 A receiving apparatus, configured to receive at least one segment data packet, and to preprocess at least one segment data packet to a data packet, comprising: a packet parser, configured to fetch at least one set of segment-packet-header information from a segment packet header of the at least one segment data packet, wherein the at least one segment data packet is a QUIC packet according to the corresponding segment-packet-header information; a data memory, configured to store the at least one segment packet header; a decrypt engine, configured to selectively decrypt an encrypted data of each segment data packet to obtain at least one QUIC private header and at least one segment payload, wherein each QUIC private header includes sequence information of the corresponding segment data packet; a transmission engine, configured to transmit the at least one segment payload to at least one specific location of a system memory; a header processing unit, configured to calculate packet information based upon the at least one QUIC private header, and to update the at least one segment packet header stored in the data memory to generate a packet header; and a controller, configured to control the transmission engine based on the sequence information to output the packet header to the system memory for generating the data packet by combining the packet header with the at least one segment payload. ### Claim 2 (depends on 1) The receiving apparatus according to claim 1, wherein the segment-packet-header information comprises at least one of a packet type, a destination address and a cyclic redundancy check (CRC) code. ### Claim 3 (depends on 1) The receiving apparatus according to claim 1, wherein the data memory stores the corresponding segment-packet-header information, and the decrypt engine decrypts the encrypted data of the one of the at least one segment data packet. ### Claim 4 (depends on 1) The receiving apparatus according to claim 1, wherein the controller determines whether to combine the at least one segment payload according to a packet index recorded in each sequence information; if the packet indices of a first segment data packet and a second segment data packet of the segment data packets are discontinuous, the controller controls the transmission engine to store a first segment payload of the first segment data packet and a second segment payload of the second segment data packet to different storage blocks of the system memory. ### Claim 5 (depends on 4) The receiving apparatus according to claim 4, wherein if the packet indices of the first segment data packet and the second segment data packet are discontinuous, the controller controls the data memory to store a first segment packet header of the first segment data packet and a second segment packet header of the second segment data packet to different storage blocks of the data memory. ### Claim 6 (depends on 1) The receiving apparatus according to claim 1, wherein the controller determines whether to combine at least one segment payload in according to a packet index recorded in each sequence information; if the packet indices of a first segment data packet and a second segment data packet of the segment data packets are continuous, the controller controls the transmission engine to combine a first segment payload of the first segment data packet and a second segment payload of the second segment data packet, and the transmission engine stores the combined payload to a storage block of the system memory. ### Claim 7 (depends on 6) The receiving apparatus according to claim 6, wherein if the packet indices of the first segment data packet and the second segment data packet are continuous, the controller combines a first segment packet header of the first segment data packet and a second segment packet header of the second segment data packet, and stores the combined packet header in a storage block of the data memory. ### Claim 8 (depends on 1) The receiving apparatus according to claim 1, wherein the header processing unit writes the at least one QUIC private header and the packet information back to the data memory to update the corresponding segment packet header stored in the data memory, wherein each packet information comprises at least one of a checksum, a packet length, a segment payload length and a byte offset. ### Claim 9 (depends on 1) The receiving apparatus according to claim 1, wherein if the controller detects the at least one segment packet header comprises an end bit, or if the controller detects the at least one segment packet header comprises the end bit and all segment packet headers stored in the data memory are combined, or if the controller detects at least one segment packet header comprising the end bit and all segment payloads stored in the system memory are combined, the controller controls the transmission engine to output the combined packet header stored in the data memory to the system memory. ### Claim 10 (depends on 1) The receiving apparatus according to claim 1, wherein after receiving the at least one segment data packet, if the receiving apparatus does not receive a next segment data packet within a preset time, the controller controls the transmission engine to output the packet header stored in the data memory to the system memory. ### Claim 11 A packet processing method, adapted for a receiving apparatus, wherein the receiving apparatus is configured to receive at least one segment data packet, and to preprocess at least one segment data packet to a data packet, and the packet processing method comprises: step A: receiving at least one segment data packet, and fetching at least one set of segment-packet-header information from a segment packet header of the at least one segment data packet; step B: storing the at least one segment packet header in a data memory of the receiving apparatus; step C: selectively decrypting an encrypted data of each segment data packet to obtain at least one QUIC private header and at least one segment payload, wherein each QUIC private header includes sequence information of the corresponding segment data packet; step D: transmitting the at least one segment payload to the at least one specific location of a system memory; step E: calculating packet information based upon the at least one QUIC private header, and updating the at least one segment packet header stored in the data memory to generate a packet header; and step F: outputting the packet header to the system memory based on the sequence information to generate the data packet by combining the packet header with the at least one segment payload, wherein the step A further comprises the following steps: step A-1: determining whether one of the at least one segment data packet is a QUIC packet according to the corresponding segment-packet-header information; and step A-2: if the one of the at least one segment data packet is the QUIC packet, storing the corresponding segment-packet-header information, and decrypting the encrypted data of the one of the at least one segment data packet. ### Claim 12 (depends on 11) The packet processing method according to claim 11, wherein the segment-packet-header information comprises at least one of a packet type, a destination address and a cyclic redundancy check (CRC) code. ### Claim 13 (depends on 11) The packet processing method according to claim 11, wherein the step D further comprises the following steps: step D-1: determining whether to combine the at least one segment payload according to a packet index recorded in each sequence information; and step D-2: if the packet indices of a first segment data packet and a second segment data packet of the segment data packets are discontinuous, controlling the transmission engine to store a first segment payload of the first segment data packet and a second segment payload of the second segment data packet to different storage blocks of the system memory. ### Claim 14 (depends on 13) The packet processing method according to claim 13, wherein the step D further comprises the following steps: step D-3: if the packet indices of the first segment data packet and the second segment data packet are discontinuous, controlling the data memory to store a first segment packet header of the first segment data packet and a second segment packet header of the second segment data packet in different storage blocks of the data memory. ### Claim 15 (depends on 11) The packet processing method according to claim 11, wherein the step D further comprises the following steps: step D-1′: determining whether to combine at least one segment payload according to a packet index recorded in each sequence information; and step D-2′: if the packet indices of a first segment data packet and a second segment data packet of the segment data packets are continuous, controlling the transmission engine to combine a first segment payload of the first segment data packet and a second segment payload of the second segment data packet, and storing the combined payload to a storage block of the system memory. ### Claim 16 (depends on 15) The packet processing method according to claim 15, wherein the step D further comprises the following steps: step D-3′: if the packet indices of the first segment data packet and the second segment data packet are continuous, combining a first segment packet header of the first segment data packet and a second segment packet header of the second segment data packet, and storing the combined packet header in a storage block of the data memory. ### Claim 17 (depends on 11) The packet processing method according to claim 11, wherein the step E further comprises the following steps: step E-1: writing the at least one QUIC private header and the packet information back to the data memory to update the corresponding segment packet header stored in the data memory, wherein each packet information comprises at least one of a checksum, a packet length, a segment payload length and a byte offset. ### Claim 18 (depends on 11) The packet processing method according to claim 11, wherein the step F further comprises the following steps: step F-1: if detecting the at least one segment packet header comprises an end bit, or if detecting the at least one segment packet header comprises the end bit and all segment packet headers stored in the data memory are combined, or if detecting the at least one segment packet header comprises the end bit and all segment payloads stored in the system memory are combined, controlling the transmission engine to output the combined packet header stored in the data memory to the system memory. ### Claim 19 (depends on 11) The packet processing method according to claim 11, wherein the step F further comprises the following steps: step F-1′: after receiving the at least one segment data packet, if the receiving apparatus does not receive a next segment data packet within a preset time, controlling the transmission engine to output the packet header stored in the data memory to the system memory.