# US 10,122,568 B2 · Digital compensation of IQ coupling in communication receivers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,122,568 B2 - Document ID: US10122568B2 - Status: Granted - Kind: B2 - Application number: 15/642,347 - Filed: 2017-07-06 - Published: 2018-01-11 - Granted: 2018-11-06 - Earliest claimed: 2016-07-07 - Assignees: Microchip Technology Incorporated - Applicants: Microchip Technology Incorporated - Inventors: Hamid Shafiee; Mohsen Pourkhaatoun; Kiran Gowda; Siddharth Shetty; Esmael Heidari; Ali Fard; Rahim Bagheri; Masoud Djafari - Web page: https://patentgrep.com/patent/US10122568B2 ## CPC - H04L 27/3863: {Compensation for quadrature error in the received signal} - H04B 1/30: for homodyne or synchrodyne receivers (demodulator circuits H03D1/22) - H04L 1/0045: {Arrangements at the receiver end} - H04L 27/22: Demodulator circuits; Receiver circuits - H04L 2027/003: {at baseband only} - H04L 2027/0038: {using an equaliser} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H04B: TRANSMISSION ## Abstract A receiver circuit includes a conversion circuit configured to down-convert a received radio-frequency signal to a baseband signal, an analog-to-digital converter configured to sample the baseband signal into a sampled signal, a Fast Fourier transform (FFT) circuit configured to perform an FFT on the sampled signal, and a digital compensation circuit configured to compensate for IQ distortion in a frequency domain. ## Claims ### Claim 1 A receiver circuit, comprising: a conversion circuit configured to down-convert a received radio-frequency signal to a baseband signal; an analog-to-digital converter configured to sample the baseband signal into a sampled complex time-domain signal; and a digital compensation circuit configured to compensate for in-phase and quadrature-phase (IQ) distortion in a frequency domain, wherein: in a first branch: the digital compensation circuit is further configured to multiply using a first multiplier circuit, the sampled complex time-domain signal by a first correction for carrier frequency offset to generate a first multiplied signal; perform a first Fast Fourier transform (FFT) on the first multiplied signal through a first FFT circuit; and the digital compensation circuit is further configured to multiply using a second multiplier circuit, a result from the first FFT with a first factor to form a first output data; in a second branch: the digital compensation circuit is further configured to multiply using a third multiplier circuit, a complex baseband the sampled complex time-domain signal by a second correction for carrier frequency offset to generate a second multiplied signal; perform a second FFT on the second multiplied signal through a second FFT circuit; perform using an inversion and conjugation circuit, conjugation by inverting and conjugating an output of the second FFT; and the digital compensation circuit is further configured to multiply using a fourth multiplier circuit, the inverted and conjugated output of the second FFT with a second factor to form a second output data; wherein, the first factor is λ1(ω)/δ and the second factor is λ2(ω)/δ, wherein λ 1 ⁡ ( ω ) = [ 1 + ω + Δω 2 ⁢ ( β 1 - β 2 ) ] , ⁢ λ 2 ⁡ ( ω ) = [ - ω + Δω 2 ⁢ ( β 1 - β 2 ) ] , ⁢ δ = λ 1 ⁡ ( ω ) ⁢ λ 1 ⁡ ( - ω - 2 ⁢ Δω ) - λ 2 ⁡ ( ω ) ⁢ λ 2 ⁡ ( - ω - 2 ⁢ Δω ) , and wherein ωΔ corresponds to a frequency offset, co corresponds to a frequency, Ts is a sampling period, and β1 and β2 are coupling coefficients; and the digital compensation circuit is further configured to add, by a summer circuit, the first output data and the second output data. ### Claim 2 (depends on 1) The receiver circuit of claim 1, wherein the first correction and the second correction are dependent upon frequency. ### Claim 3 (depends on 1) The receiver circuit of claim 1, further comprising an equalizer circuit configured to equalize a sum of the first output data and the second output data. ### Claim 4 (depends on 1) The receiver circuit of claim 1, wherein the first correction is e−ΔωcnTs, and the second correction is eΔωcnTs, wherein Δωc corresponds to a frequency offset, n is a sample index, and Ts is a sampling period. ### Claim 5 (depends on 1) The receiver circuit of claim 1, wherein the digital compensation circuit is configured to compensate for IQ distortion arising from IQ coupling after down-conversion. ### Claim 6 (depends on 1) The receiver circuit of claim 1, wherein the radio-frequency signal includes orthogonal-frequency-domain multiplexing (OFDM) packets. ### Claim 7 A system, comprising: a conversion circuit configured to down-convert a received radio-frequency signal to a baseband signal; an analog-to-digital converter configured to sample the baseband signal into a sampled complex time-domain signal; and a digital compensation circuit configured to compensate for in-phase and quadrature-phase (IQ) distortion in a frequency domain, wherein: in a first branch: the digital compensation circuit is further configured to multiply using a first multiplier circuit, the sampled complex time-domain signal by a first correction for carrier frequency offset to generate a first multiplied signal; perform a first Fast Fourier transform (FFT) on the first multiplied signal through a first FFT circuit; and the digital compensation circuit is further configured to multiply using a second multiplier circuit, a result from the first FFT with a first factor to form a first output data; in a second branch: the digital compensation circuit is further configured to multiply using a third multiplier circuit, a complex baseband the sampled complex time-domain signal by a second correction for carrier frequency offset to generate a second multiplied signal; perform a second FFT on the second multiplied signal through a second FFT circuit; perform using an inversion and conjugation circuit, conjugation by inverting and conjugating an output of the second FFT; and the digital compensation circuit is further configured to multiply using a fourth multiplier circuit, the inverted and conjugated output of the second FFT with a second factor to form a second output data; wherein, the first factor is λ1(ω) /δ and the second factor is λ2 (ω)/δ, wherein λ 1 ⁡ ( ω ) = [ 1 + ω + Δω 2 ⁢ ( β 1 - β 2 ) ] , ⁢ λ 2 ⁡ ( ω ) = [ - ω + Δω 2 ⁢ ( β 1 - β 2 ) ] , ⁢ δ = λ 1 ⁡ ( ω ) ⁢ λ 1 ⁡ ( - ω - 2 ⁢ Δω ) - λ 2 ⁡ ( ω ) ⁢ λ 2 ⁡ ( - ω - 2 ⁢ Δω ) , and wherein ωΔ corresponds to a frequency offset, ω corresponds to a frequency, Ts is a sampling period, and β1 and β2 are coupling coefficients; and the digital compensation circuit is further configured to add, by a summer circuit, the first output data and the second output data. ### Claim 8 (depends on 7) The system of claim 7, wherein the first correction and the second correction are dependent upon frequency. ### Claim 9 (depends on 7) The system of claim 7, further comprising an equalizer circuit configured to equalize a sum of the first output data and the second output data. ### Claim 10 (depends on 7) The system of circuit of claim 7, wherein the first correction is e−ΔωcnTs, and the second correction is eΔωcnTs, wherein Δωc corresponds to a frequency offset, n is a sample index, and Ts is a sampling period. ### Claim 11 (depends on 7) The system of claim 7, wherein the digital compensation circuit is configured to compensate for IQ distortion arising from IQ coupling after down-conversion. ### Claim 12 (depends on 7) The system of claim 7, wherein the radio-frequency signal includes orthogonal-frequency-domain multiplexing (OFDM) packets.