# US 10,122,561 B2 · Orthogonal differential vector signaling codes with embedded clock

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- Number: US 10,122,561 B2
- Document ID: US10122561B2
- Status: Granted
- Kind: B2
- Application number: 15/829,904
- Filed: 2017-12-02
- Published: 2018-03-29
- Granted: 2018-11-06
- Earliest claimed: 2014-08-01
- Assignees: Kandou Labs, S.A.
- Applicants: Kandou Labs, S.A.
- Inventors: Brian Holden; Amin Shokrollahi
- Web page: https://patentgrep.com/patent/US10122561B2

## CPC

- H04L 27/2637: {with direct modulation of individual subcarriers}
- G06F 13/426: {using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus}
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 7/1066: {Output synchronization}
- G11C 7/1093: {Input synchronization}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- H04L 25/4919: {using balanced multilevel codes (H04L25/4927 takes precedence)}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct but temporally aligned data and clocking signals over the same transport medium. Embodiments providing enhanced LPDDR interfaces are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.

## Claims

### Claim 1

A method comprising:
receiving, at a plurality of multi-input comparators (MICs), a set of symbols of a codeword of a vector signaling code via wires of a multi-wire bus;
generating a plurality of sub-channel data signals at a first subset of MICs of the plurality of MICs, each sub-channel data signal generated by a respective MIC of the first subset, the respective MIC applying a respective set of data input coefficients to the set of symbols of the codeword, the respective set of data input coefficients selected according to a respective row of a plurality of rows of an orthogonal matrix; and
receiving first and second subsets of symbols of the set of the symbols of the codeword of the vector signaling code at a timing MIC of the plurality of MICs, the first and second subsets of the symbols received via first and second subsets of wires of the multi-wire bus, respectively;
responsively generating, using the timing MIC, a sub-channel clock signal by applying a set of timing input coefficients to the first and second subsets of symbols of the set symbols to detect changes in common mode across the first subset of wires with respect to common mode across the second subset of wires, the changes in common mode associated with transitions in the sub-channel clock signal.

### Claim 2 (depends on 1)

The method of claim 1, further comprising sampling the plurality of sub-channel data signals according to the sub-channel clock signal.

### Claim 3 (depends on 1)

The method of claim 1, wherein the sub-channel clock signal has a ½ unit interval delay with respect to the plurality of sub-channel data signals.

### Claim 4 (depends on 1)

The method of claim 1, wherein each MIC of the plurality of MICs is connected to all wires of the multi-wire bus.

### Claim 5 (depends on 1)

The method of claim 1, wherein one or more MICs of the first subset of MICs is connected to a portion of wires of the multi-wire bus.

### Claim 6 (depends on 1)

The method of claim 1, wherein the symbols of the codeword of the vector signaling code have symbol values selected from at least a ternary alphabet.

### Claim 7 (depends on 1)

The method of claim 1, wherein the at least a ternary alphabet is a quaternary alphabet comprising a set of symbol values ±1, ±⅓.

### Claim 8 (depends on 1)

The method of claim 1, wherein the set of timing input coefficients comprises coefficients having an equal magnitude.

### Claim 9 (depends on 1)

The method of claim 1, wherein the set of data input coefficients and timing input coefficients are distinct, orthogonal permutations of a vector [+1 +1 −1 −1].

### Claim 10 (depends on 9)

The method of claim 9, wherein the vector signaling code is an Ensemble Non-Return-to-Zero (ENRZ) code.

### Claim 11

An apparatus comprising:
a plurality of data multi-input comparators (MICs) configured to receive a set of symbols of a codeword of a vector signaling code via wires of a multi-wire bus, the plurality of data MICs configured to generate a plurality of sub-channel data signals, each sub-channel data signal generated by a respective data MIC of the plurality of data MICs, the respective data MIC applying a respective set of data input coefficients to the set of symbols of the codeword, the respective set of data input coefficients selected according to a respective row of a plurality of rows of an orthogonal matrix; and
a timing MIC configured to receive first and second subsets of symbols of the set of the symbols of the codeword of the vector signaling code, the first and second subsets of the symbols received via first and second subsets of wires, respectively, the timing MIC further configured to responsively generate a sub-channel clock signal by applying a set of timing input coefficients to the first and second subsets of symbols of the set symbols to detect changes in common mode across the first subset of wires with respect to common mode across the second subset of wires, the changes in common mode associated with transitions in the sub-channel clock signal.

### Claim 12 (depends on 11)

The apparatus of claim 11, further comprising a plurality of samplers configured to sample the plurality of sub-channel data signals according to the sub-channel clock signal.

### Claim 13 (depends on 11)

The apparatus of claim 11, wherein the sub-channel clock signal has a ½ unit interval delay with respect to the plurality of sub-channel data signals.

### Claim 14 (depends on 11)

The apparatus of claim 11, wherein the plurality of data MICs and the timing MIC are connected to all wires of the multi-wire bus.

### Claim 15 (depends on 11)

The apparatus of claim 11, wherein one or more of the data MICs is connected to a portion of wires of the multi-wire bus.

### Claim 16 (depends on 11)

The apparatus of claim 11, wherein the symbols of the codeword of the vector signaling code have symbol values selected from at least a ternary alphabet.

### Claim 17 (depends on 11)

The apparatus of claim 11, wherein the at least a ternary alphabet is a quaternary alphabet comprising a set of symbol values ±1, ±⅓.

### Claim 18 (depends on 11)

The apparatus of claim 11, wherein the set of timing input coefficients comprises coefficients having an equal magnitude.

### Claim 19 (depends on 11)

The apparatus of claim 11, wherein the set of data input coefficients and timing input coefficients are distinct, orthogonal permutations of a vector [+1 +1 −1 −1].

### Claim 20 (depends on 19)

The apparatus of claim 19, wherein the vector signaling code is an Ensemble Non-Return-to-Zero (ENRZ) code.