# US 10,122,527 B1 · Signal phase tracking with high resolution, wide bandwidth and low phase noise using compound phase locked loop

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- Number: US 10,122,527 B1
- Document ID: US10122527B1
- Status: Granted
- Kind: B1
- Application number: 15/934,890
- Filed: 2018-03-23
- Granted: 2018-11-06
- Earliest claimed: 2018-03-23
- Assignees: Northrop Grumman Systems Corporation
- Applicants: Northrop Grumman Systems Corporation
- Inventors: Gerald R. Fischer
- Web page: https://patentgrep.com/patent/US10122527B1

## CPC

- H04L 7/0331: {with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence)}
- H03L 7/07: using several loops, e.g. for redundant clock signal generation
- H03L 7/0807: {concerning mainly a recovery circuit for the reference signal}
- H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00)
- H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop
- H03L 7/0994: {comprising an accumulator}
- H03L 7/1976: {using a phase accumulator for controlling the counter or frequency divider}
- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H03M 3/30: {Delta-sigma modulation}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A clock recovery circuit for providing clock recovery from a burst signal that is periodically present and absent in a noisy channel. The recovery circuit includes an outer main tracking second-order phase locked loop (PLL) having an analog phase detector, a digital loop filter, and an analog/digital hybrid numerically controlled oscillator (NCO) that operates so that the clock recovery frequency is “frozen” to its last value from the previous burst and the phase detector is disabled during the gaps between data bursts. The NCO is implemented with an inner loop PLL that operates as a high resolution synthesizer having a low internal control bandwidth that preserves VCO phase noise. The outer main loop achieves a higher control bandwidth through direct tuning of the inner loop VCO with the outer loop tuning signal.

## Claims

### Claim 1

A clock recovery circuit that recovers a timing signal from an input signal, said recovery circuit comprising:
a main phase detector responsive to the input signal and a clock recovery signal and providing a phase error signal;
a main loop filter responsive to the phase error signal and generating a tuning signal; and
a numerically controlled oscillator (NCO) circuit responsive to a reference clock signal and the tuning signal, said NCO circuit including an inner phase locked loop (PLL) having an inner phase detector generating an inner error signal in response to the reference clock signal and a feedback clock recovery signal, a feedback divider responsive to the clock recovery signal that divides the clock recovery signal by a programmable value defined by the tuning signal to generate the feedback clock recovery signal, an NCO circuit loop filter that filters the inner error signal, an NCO circuit summer that adds the filtered inner error signal and the tuning signal and provides a summed signal, and an NCO circuit controlled oscillator that is tuned by the summed signal to generate the clock recovery signal.

### Claim 2 (depends on 1)

The recovery circuit according to claim 1 wherein the NCO circuit further includes a modulator responsive to the reference clock signal and the tuning signal, said modulator generating the programmable value used to generate the feedback clock recovery signal in the feedback divider, where the programmable value can include average division ratios that can be a fraction of an integer.

### Claim 3 (depends on 2)

The recovery circuit according to claim 2 wherein the modulator is a digital sigma delta modulator.

### Claim 4 (depends on 1)

The recovery circuit according to claim 1 wherein the NCO circuit further includes a reference signal divider that divides the reference clock signal before it is provided to the inner phase detector.

### Claim 5 (depends on 1)

The recovery circuit according to claim 1 wherein the recovery circuit receives the input signal in a burst format where the input signal is periodically present and absent, said recovery circuit further comprising:
a burst detector responsive to the input signal and detecting when the input signal is being received by the recovery circuit; and
a switch responsive to the phase error signal and being closed by the burst detector in response to detecting the presence of the input signal.

### Claim 6 (depends on 5)

The recovery circuit according to claim 5 wherein the burst detector includes a burst detector PLL having a burst detector phase detector, a burst detector loop filter and a burst detector controlled oscillator.

### Claim 7 (depends on 5)

The recovery circuit according to claim 5 wherein the main loop filter is implemented digitally and the switch enables the main loop filter to respond to the input signal only during the presence of the input signal.

### Claim 8 (depends on 7)

The recovery circuit according to claim 7 further comprising an analog-to-digital (A/D) converter positioned upstream of the switch that converts the phase error signal to a digital phase error signal provided to the main loop filter.

### Claim 9 (depends on 1)

The recovery circuit according to claim 1 wherein the main loop filter includes a first multiplier that multiplies the phase error signal by a proportional gain signal to generate a proportional phase error signal, a second multiplier that multiplies the phase error signal by an integral gain signal and an accumulator for accumulating the multiplied integral signal to generate an integral phase error signal, wherein the proportional phase error signal and the integral phase error signal are added in a loop filter summer to generate the tuning signal.

### Claim 10 (depends on 9)

The recovery circuit according to claim 9 wherein the NCO circuit further includes a digital-to-analog (D/A) converter that converts the tuning signal to an analog signal before it is sent to the NCO circuit summer.

### Claim 11

A clock recovery circuit that recovers a timing signal from a bursty input signal where the input signal is periodically present and absent, said recovery circuit comprising:
a main phase detector responsive to the input signal and a clock recovery signal and providing a phase error signal;
an analog-to-digital (A/D) converter responsive to the phase error signal from the phase detector and converting the phase error signal to a digital phase error signal;
a burst detector responsive to the input signal and detecting when the input signal is being received by the recovery circuit;
a switch responsive to the digital phase error signal and being closed by the burst detector in response to detecting the presence of the input signal;
a digital main loop filter responsive to the digital phase error signal and generating a digital tuning signal; and
a numerically controlled oscillator (NCO) circuit responsive to a reference clock signal and the digital tuning signal, said NCO circuit including an inner phase locked loop (PLL) having an inner phase detector generating an inner error signal in response to the reference clock signal and a feedback clock recovery signal, a feedback divider responsive to the clock recovery signal that divides the clock recovery signal by a programmable value defined by the tuning signal to generate the feedback clock recovery signal, an NCO circuit loop filter that filters the inner error signal, a digital-to-analog (D/A) converter that converts the digital tuning signal to an analog tuning signal, an NCO circuit summer that adds the filtered inner error signal and the analog tuning signal and provides a summed signal, and an NCO circuit controlled oscillator that is tuned by the summed signal so as to generate the clock recovery signal.

### Claim 12 (depends on 11)

The recovery circuit according to claim 11 wherein the NCO circuit further includes a modulator responsive to the reference clock signal and the tuning signal, said modulator generating the programmable value used to generate the feedback clock recovery signal in the feedback divider, where the programmable value can include average division ratios that can be a fraction of an integer.

### Claim 13 (depends on 12)

The recovery circuit according to claim 12 wherein the modulator is a digital sigma delta modulator.

### Claim 14 (depends on 11)

The recovery circuit according to claim 11 wherein the NCO circuit further includes a reference signal divider that divides the reference clock signal before it is provided to the inner phase detector.

### Claim 15 (depends on 11)

The recovery circuit according to claim 11 wherein the burst detector includes a burst detector PLL having a burst detector phase detector, a burst detector loop filter and a burst detector controlled oscillator.

### Claim 16 (depends on 11)

The recovery circuit according to claim 11 wherein the main loop filter includes a first multiplier that multiplies the phase error signal by a proportional gain signal to generate a proportional phase error signal, a second multiplier that multiplies the phase error signal by an integral gain signal and an accumulator for accumulating the multiplied integral signal to generate an integral phase error signal, wherein the proportional phase error signal and the integral phase error signal are added in a loop filter summer to generate the tuning signal.