# US 10,122,526 B2 · Phase detector in a delay locked loop

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- Number: US 10,122,526 B2
- Document ID: US10122526B2
- Status: Granted
- Kind: B2
- Application number: 15/477,078
- Filed: 2017-04-01
- Published: 2018-10-04
- Granted: 2018-11-06
- Earliest claimed: 2017-04-01
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Fangxing Wei; Dan Shi; Michael J. Allen
- Web page: https://patentgrep.com/patent/US10122526B2

## CPC

- H03L 7/0812: {and where no voltage or current controlled oscillator is used}
- H03K 5/26: the characteristic being duration, interval, position, frequency, or sequence
- H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop
- H03L 7/089: the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence)
- H04L 7/0037: {Delay of clock signal}
- H04L 7/0045: {Correction by a latch cascade}
- H04L 7/027: extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
- H04L 7/0331: {with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence)}
- H04L 7/04: Speed or phase control by synchronisation signals {(H04L7/0075 takes precedence)}
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

Technology for a phase detector is described. The phase detector can include a reference clock. The phase detector can include a feedback clock. The phase detector can include a first latch operable to set a first latch output depending on a lead-lag status between the reference clock and the feedback clock. The phase detector can include a second latch that loads the lead-lag status when the reference clock and the feedback clock produce clock signals in a high state. The phase detector can include a third latch that loads the lead-lag status from the second latch when the reference clock and the feedback clock produce clock signals in a low state.

## Claims

### Claim 1

A phase detector comprising:
a reference clock;
a feedback clock;
a first latch operable to set a first latch output depending on a lead-lag status between the reference clock and the feedback clock;
a second latch that loads the lead-lag status when the reference clock and the feedback clock produce clock signals in a high state; and
a third latch that loads the lead-lag status from the second latch when the reference clock and the feedback clock produce clock signals in a low state.

### Claim 2 (depends on 1)

The phase detector of claim 1, wherein the lead-lag status indicates that the feedback clock leads the reference clock or that the feedback clock lags the reference clock.

### Claim 3 (depends on 1)

The phase detector of claim 1, wherein the second latch loads the lead-lag status in accordance with a defined time delay.

### Claim 4 (depends on 1)

The phase detector of claim 1, wherein:
the lead-lag status indicates that the feedback clock lags the reference clock, and:
the first latch output (q0/q0b) of the first latch is set to a low state when the reference clock produces clock signals transiting from a low state to high state;
a second latch output (q1/q1b) of the second latch is set to a low state when the reference clock and the feedback clock are both in high states; and
a third latch output (q2/q2b) of the third latch is set to a low state when the reference clock and the feedback clock produce clock signals in low states.

### Claim 5 (depends on 4)

The phase detector of claim 4, wherein the phase detector is configured to send a down output value of ‘1’ to a delay locked loop (DLL) state machine to decrease a delay chain delay when the third latch output (q2/q2b) is set to the low state.

### Claim 6 (depends on 1)

The phase detector of claim 1, wherein:
the lead-lag status indicates that the feedback clock leads the reference clock, and:
the first latch output (q0/q0b) of the first latch is set to a high state when the feedback clock produces clock signals transiting from a low state to high state;
a second latch output (q1/q1b) of the second latch is set to a high state when the reference clock and the feedback clock are both in high states; and
a third latch output (q2/q2b) of the third latch is set to a high state when the reference clock and the feedback clock produce clock signals in low states.

### Claim 7 (depends on 6)

The phase detector of claim 6, wherein the phase detector is configured to send an up output value of ‘1’ to a DLL state machine to increase a delay chain delay when the third latch output (q2/q2b) is set to the high state.

### Claim 8 (depends on 1)

The phase detector of claim 1, wherein a first signal load (load0) in the first latch becomes a self-timed high pulse when the reference clock and the feedback clock are high.

### Claim 9 (depends on 1)

The phase detector of claim 1, wherein a first signal load (load0) in the second latch and a second signal load (load1) in the third latch do not transit to a high state when the reference clock and the feedback clock are 180 degrees out-of-phase, and the second latch and the third latch are isolated from updates to prevent incorrect toggling.

### Claim 10 (depends on 1)

The phase detector of claim 1, wherein the first latch, the second latch and the third latch are cross coupled latches.

### Claim 11 (depends on 1)

The phase detector of claim 1, wherein the phase detector is included in a digital delay locked loop (DLL).

### Claim 12

An apparatus comprising:
a reference clock;
a feedback clock;
a first cross coupled latch operable to set a first latch output depending on a lead-lag status between the reference clock and the feedback clock, wherein the lead-lag status indicates that the feedback clock leads the reference clock or that the feedback clock lags the reference clock;
a second cross coupled latch that loads the lead-lag status when the reference clock and the feedback clock produce clock signals in a high state; and
a third cross coupled latch that loads the lead-lag status from the second cross coupled latch to the third cross coupled latch when the reference clock and the feedback clock produce clock signals in a low state.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein:
the lead-lag status indicates that the feedback clock lags the reference clock, and:
the first latch output (q0/q0b) of the first cross coupled latch is set to a low state when the reference clock produces clock signals transiting from a low state to high state;
a second latch output (q1/q1b) of the second cross coupled latch is set to a low state when the reference clock and the feedback clock are both in high states, wherein a first signal load (load0) in the first cross coupled latch loads the low state of the first latch output (q0/q0b) into the second cross coupled latch; and
a third latch output (q2/q2b) of the third cross coupled latch is set to a low state when the reference clock and the feedback clock produce clock signals in low states, wherein a second signal load (load1) in the second cross coupled latch loads the low state of the second latch output (q1/q1b) into the third cross coupled latch,
wherein the phase detector is configured to send a down output value of ‘1’ to a delay locked loop (DLL) state machine to decrease a delay chain delay when the third latch output (q2/q2b) is set to the low state.

### Claim 14 (depends on 12)

The apparatus of claim 12, wherein:
the lead-lag status indicates that the feedback clock leads the reference clock, and:
the first latch output (q0/q0b) of the first cross coupled latch is set to a high state when the feedback clock produces clock signals transiting from a low state to high state;
a second latch output (q1/q1b) of the second cross coupled latch is set to a high state when the reference clock and the feedback clock are both in high states, wherein a first signal load (load0) in the first cross coupled latch loads the high state of the first latch output (q0/q0b) into the second cross coupled latch; and
a third latch output (q2/q2b) of the third cross coupled latch is set to a high state when the reference clock and the feedback clock produces clock signals in low states, wherein a second signal load (load1) in the second cross coupled latch loads the high state of the second latch output (q1/q1b) into the third cross coupled latch,
wherein the phase detector is configured to send an up output value of ‘1’ to a delay locked loop (DLL) state machine to increase a delay chain delay when the third latch output (q2/q2b) is set to the high state.

### Claim 15 (depends on 12)

The apparatus of claim 12, wherein a first signal load (load0) in the first cross coupled latch becomes a self-timed high pulse when the reference clock and the feedback clock are high.

### Claim 16 (depends on 12)

The apparatus of claim 12, wherein a first signal load (load0) in the second cross coupled latch and a second signal load (load1) in the third cross coupled latch do not transit to a high state when the reference clock and the feedback clock are 180 degrees out-of-phase, and the second cross coupled latch and the third cross coupled latch are isolated from updates to prevent incorrect toggling.

### Claim 17 (depends on 12)

The apparatus of claim 12, wherein the apparatus is a digital phase detector in a delay locked loop (DLL).

### Claim 18

A method for performing phase detection, the method comprising:
setting, in a first latch of a phase detector, a first latch output depending on a lead-lag status between a reference clock and a feedback clock in the phase detector;
loading, in a second latch of the phase detector, the lead-lag status when the reference clock and the feedback clock produce clock signals in high states; and
loading, in a third latch of the phase detector, the lead-lag status from the second latch when the reference clock and the feedback clock produce clock signals in low states.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
when the lead-lag status indicates that the feedback clock lags the reference clock:
setting the first latch output (q0/q0b) of the first latch to a low state when the reference clock produces clock signals transiting from a low state to high state;
setting a second latch output (q1/q1b) of the second latch to a low state when the reference clock and the feedback clock produce clock signals in high states; and
setting a third latch output (q2/q2b) of the third latch to a low state when the reference clock and the feedback clock produce clock signals in low states.

### Claim 20 (depends on 19)

The method of claim 19, further comprising sending a down output value of ‘1’ to a delay locked loop (DLL) state machine to decrease a delay chain delay when the third latch output (q2/q2b) is set to the low state.

### Claim 21 (depends on 18)

The method of claim 18, further comprising:
when the lead-lag status indicates that the feedback clock leads the reference clock:
setting the first latch output (q0/q0b) of the first latch to a high state when the feedback clock produces clock signals transiting from a low state to high state;
setting a second latch output (q1/q1b) of the second latch to a high state when the reference clock and the feedback clock produce clock signals in high states; and
setting a third latch output (q2/q2b) of the third latch to a high state when the reference clock and the feedback clock produce clock signals in low states.

### Claim 22 (depends on 21)

The method of claim 21, further comprising sending an up output value of ‘1’ to a delay locked loop (DLL) state machine to increase a delay chain delay when the third latch output (q2/q2b) is set to the high state.

### Claim 23 (depends on 18)

The method of claim 18, wherein the phase detection is performed using the phase detector in a delay locked loop (DLL).