# US 10,122,525 B2 · Method and apparatus for performing a holdover function on a holdover line card

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- Number: US 10,122,525 B2
- Document ID: US10122525B2
- Status: Granted
- Kind: B2
- Application number: 15/456,211
- Filed: 2017-03-10
- Published: 2018-09-13
- Granted: 2018-11-06
- Earliest claimed: 2017-03-10
- Assignees: Nokia of America Corporation
- Applicants: Simon P. Creasy; Steven G. Driediger
- Inventors: Simon P. Creasy; Steven G. Driediger
- Web page: https://patentgrep.com/patent/US10122525B2

## CPC

- H04J 3/0688: {Change of the master or reference, e.g. take-over or failure of the master}
- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H03L 7/07: using several loops, e.g. for redundant clock signal generation
- H03L 7/14: for assuring constant frequency when supply or correction voltages fail
- H03L 7/143: {by switching the reference signal of the phase-locked loop}
- H03L 7/22: using more than one loop
- H04L 5/0048: {Allocation of pilot signals, i.e. of signals known to the receiver (allocation of control signalling H04L5/0053; use of control signalling H04L5/0091)}
- H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

Various embodiments relate to a network node and method thereof including a high stability oscillator and a holdover phase-locked loop (“PLL”) wherein the holdover PLL is configured to perform a holdover function by receiving a system clock signal, disciplining the high stability oscillator using the system clock signal to generate a local reference signal, and providing the local reference signal as the system clock signal when the system clock signal becomes unavailable.

## Claims

### Claim 1

A network node, comprising:
a timing circuit comprising a phase lock loop (“PLL”) and a first oscillator, wherein the PLL is configured to generate a system clock signal based on source timing information and an output of the first oscillator;
a holdover circuit comprising a second oscillator, the second oscillator having higher stability than the first oscillator, the holdover circuit using the system clock signal from the timing circuit to discipline the second oscillator and generate a local reference clock signal,
wherein the local reference clock signal is used as the source timing information for the timing circuit to generate a disciplined system clock signal in response to which the holdover circuit does not discipline using the disciplined system clock signal.

### Claim 2 (depends on 1)

The network node of claim 1, further comprising:
reverting back to the system clock signal based on source timing information.

### Claim 3 (depends on 1)

The network node of claim 1, wherein the system clock signal is received from a synchronous equipment timing source (“SETS”) PLL on a timing circuit.

### Claim 4 (depends on 3)

The network node of claim 3, wherein the local reference clock signal is provided from the holdover circuit to the timing circuit.

### Claim 5 (depends on 1)

The network node of claim 1, further comprising the holdover circuit:
determining whether the system clock signal has become unavailable.

### Claim 6 (depends on 3)

The network node of claim 3, further comprising the holdover circuit:
locking the SETS PLL on the timing circuit to the local reference clock signal.

### Claim 7 (depends on 3)

The network node of claim 3, wherein the system clock signal is transmitted from a fanout on the timing circuit to the holdover circuit.

### Claim 8 (depends on 3)

The network node of claim 3, wherein the local reference clock signal is transmitted from the holdover circuit to a selector on the timing circuit.

### Claim 9 (depends on 3)

The network node of claim 3, wherein the second oscillator is a temperature-compensated crystal oscillator, an oven controlled crystal oscillator, a double oven controlled crystal oscillator, an atomic clock or any oscillator which has a higher stability than the first oscillator.

### Claim 10 (depends on 3)

The network node of claim 3, wherein the second oscillator is positioned external to the holdover circuit and connected to the holdover circuit to achieve the same effect as if positioned on the holdover circuit.

### Claim 11

A method for performing a holdover function on a network node, comprising the steps of:
generating a system clock signal, by a phase lock loop (“PLL”) on a timing circuit including and a first oscillator, based on source timing information and an output of the first oscillator;
disciplining, by a holdover circuit including a second oscillator, the second oscillator having higher stability than the first oscillator, the second oscillator using the system clock signal from the timing circuit and generating a local reference clock signal,
wherein the local reference clock signal is used as the source timing information for the timing circuit to generate a disciplined system clock signal in response to which the holdover circuit does not discipline using disciplined the system clock signal.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
reverting back to the system clock signal based on source timing information.

### Claim 13 (depends on 11)

The method of claim 11, wherein the system clock signal is received from a synchronous equipment timing source (“SETS”) PLL on a timing circuit.

### Claim 14 (depends on 13)

The method of claim 13, wherein the local reference clock signal is provided from the holdover circuit to the timing circuit.

### Claim 15 (depends on 11)

The method of claim 11, further comprising:
determining whether the system clock signal has become unavailable.

### Claim 16 (depends on 13)

The method of claim 13, further comprising:
locking the SETS PLL on the timing circuit to the local reference clock signal.

### Claim 17 (depends on 13)

The method of claim 13, wherein the system clock signal is transmitted from a fanout on the timing circuit to the holdover circuit.

### Claim 18 (depends on 13)

The method of claim 13, wherein the local reference clock signal is transmitted from the holdover circuit to a selector on the timing circuit.

### Claim 19 (depends on 13)

The method of claim 13, wherein the second oscillator is a temperature-compensated crystal oscillator, an oven controlled crystal oscillator, a double oven controlled crystal oscillator, an atomic clock or any oscillator which has a higher stability than the first oscillator.

### Claim 20 (depends on 13)

The method of claim 13, wherein the second oscillator is positioned external to the holdover circuit and connected to the holdover circuit to achieve the same effect as if positioned on the holdover circuit.