# US 10,122,524 B2 · Timing correction in a communication system

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- Number: US 10,122,524 B2
- Document ID: US10122524B2
- Status: Granted
- Kind: B2
- Application number: 15/899,658
- Filed: 2018-02-20
- Published: 2018-06-21
- Granted: 2018-11-06
- Earliest claimed: 2016-06-17
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Anant Shankar Kamath; Divyasree J.
- Web page: https://patentgrep.com/patent/US10122524B2

## CPC

- B60Q 1/0483: {mounted on a bracket, e.g. details concerning the mouting of the lamps on the vehicle body}
- B60Q 1/0029: {Spatial arrangement}
- B60Q 1/0094: {Arrangement of electronic circuits separated from the light source, e.g. mounting of housings for starter circuits for discharge lamps (arrangements being part of the light source holder F21V17/06, F21S43/195)}
- F21S 45/43: using gas
- F21S 45/49: Attachment of the cooling means
- H04L 7/0037: {Delay of clock signal}
- H04L 7/0087: {Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection}
- H04L 25/0266: {Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling}
- H04L 25/0292: {Arrangements specific to the receiver end}
- H04L 25/085: {Arrangements for reducing interference in line transmission systems, e.g. by differential transmission}
- H10W 40/641: {Snap-on arrangements, e.g. clips}
- B60Q: ARRANGEMENT OF SIGNALLING OR LIGHTING DEVICES, THE MOUNTING OR SUPPORTING THEREOF OR CIRCUITS THEREFOR, FOR VEHICLES IN GENERAL
- F21S: NON-PORTABLE LIGHTING DEVICES; SYSTEMS THEREOF; VEHICLE LIGHTING DEVICES SPECIALLY ADAPTED FOR VEHICLE EXTERIORS
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

One example includes a communication system. The system includes a data transmitter configured to generate a digital communication signal and a data receiver configured to receive the digital communication signal. The system also includes a pulse-width distortion (PWD) correction circuit arranged between the data transmitter and the data receiver and being configured to adjust at least one timing parameter associated with the communication signal.

## Claims

### Claim 1

A pulse-width distortion (PWD) correction circuit comprising at least one edge-delay circuit, each of the at least one edge-delay circuit comprising:
a buffer configured to generate a buffered digital communication signal based on a digital communication signal, the buffer comprising an inverter stage configured to invert the digital communication signal;
a filter configured to generate an average voltage corresponding to an average amplitude of the buffered digital communication signal; and
an error amplifier configured to compare the average voltage with a predetermined reference voltage to generate a comparison signal that controls the inverter stage of the buffer in a negative feedback arrangement.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein the inverter stage comprises a delay transistor interconnecting one transistor of an inverting transistor pair and a respective one of a high-voltage rail and a low-voltage rail, the delay transistor being controlled by the comparison signal to delay a respective one of a rising-edge and a falling-edge of the buffered digital communication signal.

### Claim 3 (depends on 2)

The circuit of claim 2, wherein the at least one edge-delay circuit comprises a rising-edge delay circuit configured to delay the rising-edge of the buffered digital communication signal and a falling edge-delay circuit configured to delay a falling-edge of the buffered digital communication signal.

### Claim 4 (depends on 1)

The circuit of claim 1, wherein the predetermined reference voltage has an amplitude equal to approximately half an amplitude of the digital communication signal in a logic-high state.

### Claim 5 (depends on 1)

The circuit of claim 1, wherein the PWD correction circuit further comprises a calibration detector configured to detect an uncalibrated state of the PWD correction circuit based on the digital communication signal and to provide a gated signal to a data receiver.

### Claim 6 (depends on 5)

The circuit of claim 5, wherein the calibration detector comprises:
an edge-detector configured to detect an edge-transition associated with the digital communication signal; and
a delay circuit configured to activate a calibration signal, the calibration signal being configured to switch a multiplexer from a first input associated with a gating signal to a second input associated with the digital communication signal in response to the edge-detector detecting the edge-transition.