# US 10,122,486 B2 · Method for clock synchronization between two devices connected by an ethernet wire connection

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- Number: US 10,122,486 B2
- Document ID: US10122486B2
- Status: Granted
- Kind: B2
- Application number: 14/522,507
- Filed: 2014-10-23
- Published: 2015-04-30
- Granted: 2018-11-06
- Earliest claimed: 2013-10-25
- Assignees: Thales
- Applicants: Thales
- Inventors: Jean-Yves Philippe; Olivier Pierrelee
- Web page: https://patentgrep.com/patent/US10122486B2

## CPC

- H04J 3/0667: {Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays (arrangements for monitoring round trip delays in packet switching networks H04L43/0864)}
- H04J 3/0658: {Clock or time synchronisation among packet nodes}
- H04N 21/8547: involving timestamps for synchronizing content
- H04J 3/0635: {Clock or time synchronisation in a network (timer in protocols H04L69/28)}
- H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S)
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

A method and system is provided for clock synchronization between two devices comprising a clock. The method comprises the following steps: a step of determining a duration necessary for transmission of a data packet between the two devices, a step of sending by one of the devices a data packet containing a sending time of this packet, and a step of determining the time by the other device by adding the transmission duration to the sending time of the packet.

## Claims

### Claim 1

A method for clock synchronization between two devices connected by an Ethernet wire connection and comprising a clock, comprising the following steps:
a step of determining a duration TL necessary for transmission of a data packet between the two devices via the Ethernet wire connection, comprising:
a step of sending a first data packet by one of the devices, requesting the other device to send a second data packet in return, and of saving a sending time tsend, by one of the devices,
a step of reception of said first data packet by the other device,
a step of sending a second data packet by the other device, which contains an indication of a duration of a processing operation TLDPG separating the reception of the first data packet and the sending of the second data packet,
a step of reception of the second data packet and of saving a reception time trecep of the second data packet by the device,
a step of determining the transmission duration on a basis of the sending time, the reception time and the processing duration using the following equation:
TL=(trecep−tsend−TLDPG)/2
a step of sending by one of the devices a third data packet containing a sending time of this third data packet, and
a step of determining a reception time of the third data packet, by the other device by adding the transmission duration to the sending time of the third data packet, and synchronizing the clock of the other device over the reception time of the third data packet,
said steps of determining a duration, sending by one of the devices a data packet and determining the time by the other device are implemented utilizing a circuit that transmits and receives Ethernet MAC frame packets.

### Claim 2 (depends on 1)

A system comprising two devices connected by an Ethernet wire connection, said devices comprising:
a programmable logic circuit configured for carrying out the clock synchronization method according to claim 1, and
a clock.

### Claim 3 (depends on 2)

The system according to claim 2, wherein said data packets exchanged between the said devices are generated by an MAC layer.

### Claim 4 (depends on 2)

The system according to claim 2, wherein said clocks of said devices are based on incrementing a counter at a rate of a clock used by said Ethernet connection.

### Claim 5 (depends on 2)

The system according to claim 2, wherein the programmable logic circuit comprises at least one of the following: a Field-Programmable Gate Array (FPGA) or an Application-Specific Integrated Circuit (ASIC).

### Claim 6 (depends on 1)

The clock synchronization method according to claim 1, further comprising implementing in each of the devices a programmable logic circuit configured to carry out the clock synchronization.

### Claim 7 (depends on 6)

The clock synchronization method according to claim 6, wherein the programmable logic circuit comprises at least one of the following: a Field-Programmable Gate Array (FPGA) or an Application-Specific Integrated Circuit (ASIC).

### Claim 8 (depends on 1)

The clock synchronization method according to claim 1, further comprising incrementing a counter of the clocks of the devices at a rate of a clock used by said Ethernet connection.

### Claim 9

A method for clock synchronization between two devices connected by an Ethernet wire connection and comprising a clock, comprising the following steps:
a step of determining a duration TL necessary for transmission of a data packet between the two devices via the Ethernet wire connection, comprising:
a step of sending a first data packet by one of the devices, requesting the other device to send a second data packet in return, and of saving a sending time tsend, by one of the devices,
a step of reception of said first data packet by the other device,
a step of sending a second data packet by the other device, which contains an indication of a duration of a processing operation TLDPG separating the reception of the first data packet and the sending of the second data packet,
a step of reception of the second data packet and of saving a reception time trecep of the second data packet by the device,
a step of determining the transmission duration on a basis of the sending time, the reception time and the processing duration using the following equation:
TL=(trecep−tsend−TLDPG)/2
a step of sending by one of the devices a third data packet containing a sending time of this third data packet,
a step of determining a reception time of the third data packet, by the other device by adding the transmission duration to the sending time of the third data packet, and
synchronizing the clock of the other device over the reception time of the third data packet,
wherein said steps of determining a duration, sending by one of the devices a data packet, and determining the time by the other device are implemented using Ethernet MAC frame packets.

### Claim 10 (depends on 9)

The clock synchronization method according to claim 9, further comprising implementing in each of the devices a programmable logic circuit configured for carrying out the clock synchronization.

### Claim 11 (depends on 10)

The clock synchronization method according to claim 10, wherein the programmable logic circuit comprises at least one of the following: a Field-Programmable Gate Array (FPGA) or an Application-Specific Integrated Circuit (ASIC).

### Claim 12 (depends on 9)

The clock synchronization method according to claim 9, further comprising incrementing a counter of the clocks of the devices at a rate of a clock used by said Ethernet connection.